Patents by Inventor Steven M. Emerson
Steven M. Emerson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130311696Abstract: An SSD controller with two SAS interfaces includes an internal switch or expander to allow the SSD controller to function as both an initiator and target. Data packets received through one of the SAS interfaces may be directed to solid state memory elements directly connected to the SSD controller, or to one or more devices connected to the other SAS interface.Type: ApplicationFiled: May 18, 2012Publication date: November 21, 2013Applicant: LSI CorporationInventors: Gregory L. Huff, Robert E. Ober, Steven M. Emerson
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Patent number: 7793008Abstract: A system comprising a plurality of controller circuits, a plurality of line buffer circuits and an arbiter. The plurality of control circuits may each be configured to store data. The plurality of line buffer circuits may each be configured to transfer data between an accessed one of the controller circuits and one of a plurality of first busses. The arbiter circuit may be configured to control access to the controller circuits by the line buffer circuits.Type: GrantFiled: April 11, 2006Date of Patent: September 7, 2010Assignee: LSI CorporationInventors: Gregory F. Hammitt, John M. Nystuen, Steven M. Emerson
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Patent number: 7620743Abstract: A reusable software block is adapted to control multiple instantiations of a peripheral device within a system. A device hardware abstraction layer defines offset values for registers of the peripheral device and a data structure for the peripheral device. A platform hardware abstraction layer defines an address map of the system, and is adapted to initialize each instantiation of the peripheral device via calls to the device hardware abstraction layer.Type: GrantFiled: April 1, 2004Date of Patent: November 17, 2009Assignee: LSI CorporationInventors: Judy M. Gehman, Matthew D. Kirkwood, Steven M. Emerson
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Patent number: 7366862Abstract: A method and apparatus are provided for interfacing with a synchronous dynamic memory in which memory commands are provided to the memory. The memory is accessed in response to the memory commands. Read data is captured in a data capture circuit having a delay setting. The delay setting is updated in response to detection of a period of read inactivity of the memory.Type: GrantFiled: November 12, 2004Date of Patent: April 29, 2008Assignee: LSI Logic CorporationInventors: John M. Nystuen, Steven M. Emerson, Stefan Auracher
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Patent number: 7257673Abstract: A circuit comprising a plurality of first line buffers, an arbiter and a cache. The plurality of first line buffers may be configured to communicate on a plurality of first busses. The arbiter may be configured to perform an arbitration among the first line buffers. The cache block may be configured to (i) determine a particular policy of a plurality of policies in response to a first transaction request from one of the first line buffers winning the arbitration and (ii) generate a second transaction request based upon the first transaction request and the particular policy.Type: GrantFiled: January 5, 2006Date of Patent: August 14, 2007Assignee: LSI CorporationInventors: Steven M. Emerson, Balraj Singh
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Patent number: 7206891Abstract: A memory controller system is provided, which includes a plurality of system buses, a multi-port memory controller and a plurality of error correcting code (ECC) encoders. The memory controller has a plurality of system bus ports and a memory port. Each ECC encoder is coupled between a respective system bus and a respective system bus port of the memory controller.Type: GrantFiled: September 26, 2002Date of Patent: April 17, 2007Assignee: LSI Logic CorporationInventors: Steven M. Emerson, Gregory F. Hammitt
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Patent number: 7114041Abstract: A circuit generally comprising a command buffer and a read buffer is disclosed. The command buffer may be configured to (i) buffer a plurality of read commands received by the circuit, wherein each read command has one of a plurality of port values and one of a plurality of identification values and (ii) transmit a tag signal from the circuit in response to servicing a particular read command of the read commands. The tag signal may have a particular port value of the port values and a particular identification value of the identification values as determined by the particular read command. The read buffer may be configured to transmit a read signal within a plurality of first transfers from the circuit in response to servicing the particular read command.Type: GrantFiled: December 20, 2002Date of Patent: September 26, 2006Assignee: LSI Logic CorporationInventors: Gregory F. Hammitt, John M. Nystuen, Steven M. Emerson
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Patent number: 7099983Abstract: A communications module for a data communications system having a plurality of data processors comprises a plurality of ports, each coupled to a respective one of the data processors. An address table associates addresses of a memory space to addresses of the data processors. The memory space may include addressable FIFOs, SRAM memory and/or flag registers. In the case of FIFOs, a counter coupled to the FIFO supplies a flag or ready signal indicating the not-full or not-empty status of the respective FIFO, which is supplied to a master device that is writing data to the FIFO or that is reading data from the FIFO so that the writing master device will write only when the FIFO is not full and the reading master device will read only when the FIFO is not empty.Type: GrantFiled: November 25, 2002Date of Patent: August 29, 2006Assignee: LSI Logic CorporationInventors: Steven M. Emerson, Gregory F. Hammitt, Steven G. Kopacek
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Patent number: 7039756Abstract: A method of operating a circuit is disclosed. The method generally comprises the steps of (A) generating a particular policy of a plurality of policies by a lookup operation on a first transaction request received by the circuit, (B) generating a second transaction request for use by a memory external to the circuit based upon the first transaction request and the particular policy in response to a first cache signal of the first transaction request having a non-cacheable state and (C) searching a plurality of address tags for cache data cached within the circuit for a match with the first transaction request in response to the first cache signal having a cacheable state.Type: GrantFiled: April 28, 2003Date of Patent: May 2, 2006Assignee: LSI Logic CorporationInventors: Steven M. Emerson, Balraj Singh
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Patent number: 7007108Abstract: A method for resource notification is disclosed. The method generally comprises the steps of (A) buffering a plurality of messages received from a plurality of busses, (B) arbitrating among the messages, (C) writing the messages in response to the arbitration, and (D) generating a plurality of notification signals on a plurality of lines in response to the messages as written to a plurality of addresses.Type: GrantFiled: April 30, 2003Date of Patent: February 28, 2006Assignee: LSI Logic CorporationInventors: Steven M. Emerson, Gregory F. Hammitt, Steven G. Kopacek
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Patent number: 7000045Abstract: A data bus system transfers words and word portions on a data bus between master devices and slave devices. A size bus carries a size code in fixed-byte format that identifies a number of bytes being transferred in one or more words and/or word portions of a transaction. A byte-enable bus carries a byte-enable code that identifies valid bytes of a word. An interface decodes the byte-enable codes to size codes and, where an odd-byte byte-enable code is decoded, it decodes the odd-byte byte-enable code to a plurality of size codes.Type: GrantFiled: August 28, 2002Date of Patent: February 14, 2006Assignee: LSI Logic CorporationInventors: Jeffrey J. Holm, Steven M. Emerson, Matthew D. Kirkwood
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Publication number: 20040221246Abstract: A method for resource notification is disclosed. The method generally comprises the steps of (A) buffering a plurality of messages received from a plurality of busses, (B) arbitrating among the messages, (C) writing the messages in response to the arbitration, and (D) generating a plurality of notification signals on a plurality of lines in response to the messages as written to a plurality of addresses.Type: ApplicationFiled: April 30, 2003Publication date: November 4, 2004Applicant: LSI LOGIC CORPORATIONInventors: Steven M. Emerson, Gregory F. Hammitt, Steven G. Kopacek
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Publication number: 20040215893Abstract: A method of operating a circuit is disclosed. The method generally comprises the steps of (A) generating a particular policy of a plurality of policies by a lookup operation on a first transaction request received by the circuit, (B) generating a second transaction request for use by a memory external to the circuit based upon the first transaction request and the particular policy in response to a first cache signal of the first transaction request having a non-cacheable state and (C) searching a plurality of address tags for cache data cached within the circuit for a match with the first transaction request in response to the first cache signal having a cacheable state.Type: ApplicationFiled: April 28, 2003Publication date: October 28, 2004Applicant: LSI LOGIC CORPORATIONInventors: Steven M. Emerson, Balraj Singh
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Publication number: 20040123036Abstract: A circuit generally comprising a command buffer and a read buffer is disclosed. The command buffer may be configured to (i) buffer a plurality of read commands received by the circuit, wherein each read command has one of a plurality of port values and one of a plurality of identification values and (ii) transmit a tag signal from the circuit in response to servicing a particular read command of the read commands. The tag signal may have a particular port value of the port values and a particular identification value of the identification values as determined by the particular read command. The read buffer may be configured to transmit a read signal within a plurality of first transfers from the circuit in response to servicing the particular read command.Type: ApplicationFiled: December 20, 2002Publication date: June 24, 2004Applicant: LSI LOGIC CORPORATIONInventors: Gregory F. Hammitt, John M. Nystuen, Steven M. Emerson
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Publication number: 20040103230Abstract: A communications module for a data communications system having a plurality of data processors comprises a plurality of ports, each coupled to a respective one of the data processors. An address table associates addresses of a memory space to addresses of the data processors. The memory space may include addressable FIFOs, SRAM memory and/or flag registers. In the case of FIFOs, a counter coupled to the FIFO supplies a flag or ready signal indicating the not-full or not-empty status of the respective FIFO, which is supplied to a master device that is writing data to the FIFO or that is reading data from the FIFO so that the writing master device will write only when the FIFO is not full and the reading master device will read only when the FIFO is not empty.Type: ApplicationFiled: November 25, 2002Publication date: May 27, 2004Inventors: Steven M. Emerson, Gregory F. Hammitt, Steven G. Kopacek
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Publication number: 20040064646Abstract: A memory controller system is provided, which includes a plurality of system buses, a multi-port memory controller and a plurality of error correcting code (ECC) encoders. The memory controller has a plurality of system bus ports and a memory port. Each ECC encoder is coupled between a respective system bus and a respective system bus port of the memory controller.Type: ApplicationFiled: September 26, 2002Publication date: April 1, 2004Inventors: Steven M. Emerson, Gregory F. Hammitt
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Publication number: 20040044812Abstract: A data bus system transfers words and word portions on a data bus between master devices and slave devices. A size bus carries a size code in fixed-byte format that identifies a number of bytes being transferred in one or more words and/or word portions of a transaction. A byte-enable bus carries a byte-enable code that identifies valid bytes of a word. An interface decodes the byte-enable codes to size codes and, where an odd-byte byte-enable code is decoded, it decodes the odd-byte byte-enable code to a plurality of size codes.Type: ApplicationFiled: August 28, 2002Publication date: March 4, 2004Inventors: Jeffrey J. Holm, Steven M. Emerson, Matthew D. Kirkwood
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Patent number: 6633944Abstract: A bus bridge generally comprising a first interface, a second interface, a plurality of registers and a controller. The first interface may be connectable to a first bus having a first data width. The second interface may be connectable to a second bus having a second data width narrower than the first data width. The plurality of registers may be configured to buffer (i) data, (ii) an address, and (iii) a plurality of control signals between the first bus and the second bus. The controller configured to control the registers.Type: GrantFiled: October 31, 2001Date of Patent: October 14, 2003Assignee: LSI Logic CorporationInventors: Jeffrey J. Holm, Steven M. Emerson, Matthew D. Kirkwood
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Patent number: 6496517Abstract: A system, such as an AMBA based system, wherein an interrupt controller is coupled directly to a processor, thereby providing that the processor can access the interrupt controller without having to access a system bus. Specifically, the interrupt controller may be coupled to a port of the processor, such as a tightly coupled memory (TCM) port or a coprocessor port of the processor. The interrupt controller may be coupled to the TCM port along with SRAM.Type: GrantFiled: November 21, 2001Date of Patent: December 17, 2002Assignee: LSI Logic CorporationInventors: Judy M. Gehman, Steven M. Emerson