Abstract: A fail-safe counter evaluator is provided to insure proper counting operations by fail-safe counters. The failsafe counter evaluator comprises a first microprocessor, a first counter, a second counter, a second microprocessor and a test channel. The first counter is configured as a counter in operation and disposed in the first microprocessor to receive externally generated count pulses. The second counter is disposed in the first microprocessor and configured to undergo a test. The test channel is configured to send an input test signal to the second counter based on test pulses from the second microprocessor. The first microprocessor and the second microprocessor are synchronized so that to coordinate a start and an end of the test. The second counter is evaluated after the test pulses have been sent to determine if the second counter is operating properly.

Abstract: A fail-safe counter evaluator is provided to insure proper counting operations by fail-safe counters. The failsafe counter evaluator comprises a first microprocessor, a first counter, a second counter, a second microprocessor and a test channel. The first counter is configured as a counter in operation and disposed in the first microprocessor to receive externally generated count pulses. The second counter is disposed in the first microprocessor and configured to undergo a test. The test channel is configured to send an input test signal to the second counter based on test pulses from the second microprocessor. The first microprocessor and the second microprocessor are synchronized so that to coordinate a start and an end of the test. The second counter is evaluated after the test pulses have been sent to determine if the second counter is operating properly.

Abstract: Certain exemplary embodiments can provide a system, which can comprise a programmable logic controller (PLC). The system can comprise a serial communications port connected to the PLC. In certain exemplary embodiments, the system can comprise a controller adapted to enable a customer application program to access and control the serial communications port.

Abstract: Certain exemplary embodiments can provide a system, which can comprise a programmable logic controller (PLC). The system can comprise a serial communications port connected to the PLC. In certain exemplary embodiments, the system can comprise a controller adapted to enable a customer application program to access and control the serial communications port.

Abstract: A serial access, electrically erasable, programmable read-only memory (EEPROM) is used to store user program and data and is disposed in a memory cartridge. The memory cartridge cooperates a base or master Programmable Logic Controller (PLC) and may be used to download a program into one or more master PLC's, or to upload a program from a master PLC to memory cartridge. Each PLC may include at least one input terminal and at least one output terminal for receiving and transmitting signals, at least one microprocessor, at least one memory device, and a connector for accessing the at least one memory device.