Abstract: In certain examples an integrated circuit protection circuit can include a circuit module, and an isolation device. The isolation device can be configured to couple a ground node of the circuit module to a power ground in an on state, and to isolate the ground node of the circuit module from the power ground in an off state, wherein the isolation module is configured to enter the off state when the IC receives a negative input voltage.

Abstract: In certain examples an integrated circuit protection circuit can include a circuit module, and an isolation device. The isolation device can be configured to couple a ground node of the circuit module to a power ground in an on state, and to isolate the ground node of the circuit module from the power ground in an off state, wherein the isolation module is configured to enter the off state when the IC receives a negative input voltage.

Abstract: A process for forming a bipolar transistor where the doping implantation of the extrinsic base regions does not affect the emitter doping levels. The techniques is to not remove the photoresist layer used to define the poly emitter contact. The photoresist layer for defining the extrinsic base regions overlays the photoresist layer over the emitter poly. When the base photoresist is processed to expose the base regions the photoresist over the emitter poly remains in tact. In this arrangement the base implantation is prevented from driving through the emitter poly and affecting the doping levels in the emitter.

Abstract: An emitter stack for a quasi-self-aligned bipolar (NPN or PNP) transistor is formed where two layers over the emitter of a silicon substrate are windowed in a manner to under cut the top layer thereby exposing the substrate material. The emitter polysilicon structure is then formed over the window and conformally extends into the undercut region thereby widening the emitter region and so reducing the distance between the edge of the emitter and the extrinsic base (the base link distance) and therefore reducing the total base resistance of the transistor.

Abstract: A structure of and a method for making an isolated NMOS transistor using standard BiCMOS processing steps and techniques. No additional masks and processing steps are needed for the isolated NMOS device relative to the standard process flow. A P-type substrate with an overlaying buried N-type layer overlaid with a buried p-type layer below a P-well is shown. An N-type region surrounds and isolates the P-well from other devices on the same wafer. N+ regions are formed in the p-well for the source and drain connections and poly or other such electrical conductors are formed on the gate, drain and source structures to make the NMOS device operational. Parasitic bipolar transistors are managed by the circuit design, current paths and biasing to ensure the parasitic bipolar transistors do not turn on.

Abstract: An emitter stack for a quasi-self-aligned bipolar (NPN or PNP) transistor is formed where two layers over the emitter of a silicon substrate are windowed in a manner to under cut the top layer thereby exposing the substrate material. The emitter polysilicon structure is then formed over the window and conformally extends into the undercut region thereby widening the emitter region and so reducing the distance between the edge of the emitter and the extrinsic base (the base link distance) and therefore reducing the total base resistance of the transistor.

Abstract: A resistor structure is disclosed that is constructed out of two layers of polysilicon. The intrinsic device is made using the top layer which is either a dedicated deposition, or formed as part of an existing process step such as a base epi growth in a BiCMOS flow. This poly layer can be made with a relatively high (greater than 2000 ohms per square) sheet resistance by appropriate scaling of the implant dose or by insitu doping methods. The resistor ends are formed by the addition of a bottom poly layer in a self aligned manner with a deposition which may already be part of the process sequence. The end result is that the intrinsic resistor body is formed of a single poly layer, while the ends are created out of two layers. These ends are thick enough so that standard silicide and contact etch processing may be added to the structure without special care.

Abstract: A well tap for a field effect device formed using a single polysilicon process and a silicide layer is provided. The polysilicon layer which makes contact to the well is doped the same way as the well but is doped opposite of the source or drain. The silicide layer is formed on the upper and sidewall surfaces of the source or drain, well tap, and gate contacts for a field effect device. The silicide layer extends from the sidewall silicide across the upper surface of the transistors and up to the sidewall oxide of the transistor gates. The structure makes it possible to eliminate laterally-spaced separate well taps used in previous devices. Elimination of the laterally-spaced well taps permits higher packing density, and lowers buried layer-to-substrate capacitance.

Abstract: A well tap for a field effect device formed using a single polysilicon process and a silicide layer is provided. The polysilicon layer which makes contact to the well is doped the same way as the well but is doped opposite of the source or drain. The silicide layer is formed on the upper and sidewall surfaces of the source or drain, well tap, and gate contacts for a field effect device. The silicide layer extends from the sidewall silicide across the upper surface of the transistors and up to the sidewall oxide of the transistor gates. The structure makes it possible to eliminate laterally-spaced separate well taps used in previous devices. Elimination of the laterally-spaced well taps permits hgher packing density, and lowers buried layer-to-substrate capacitance.