Abstract: Substrate precursor structures include a substrate blank having at least one aperture extending substantially through the substrate blank. At least a portion of at least one conductive layer covers a surface of the at least one aperture of the substrate blank. A mask pattern covers a portion of the at least one conductive layer and exposes another portion of the at least one conductive layer to define at least one conductive element, at least a portion of which extends over the surface of the at least one aperture.

Abstract: A method of fabricating a substrate is disclosed. Apertures are formed in a substrate blank. A conductive layer is formed on opposing surfaces of the substrate, as well as inside the apertures. Conductive elements are defined on one or both opposing surfaces by masking and etching. Additional layers of conductive materials may be used to provide a barrier layer and a noble metal cap for the conductive elements. The methods of the present invention may be used to fabricate an interposer for use in packaging semiconductor devices or a test substrate. Substrate precursor structures are also disclosed.

Abstract: Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed in place to form a layer lining the via. The lined via may then be filled with a desired material. For example, a via lined with an insulative material may be filled with a material such as copper to create an insulated conductive via through the substrate.

Abstract: The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the invention includes methods in which one or more processing steps associated with fabrication and patterning of bond pads and redistribution layers is conducted simultaneously over a fuse box region to form and/or remove materials that are directly over the fuse box region.

Abstract: Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed in place to form a layer lining the via. The lined via may then be filled with a desired material. For example, a via lined with an insulative material may be filled with a material such as copper to create an insulated conductive via through the substrate.

Abstract: A semiconductor component configured for wafer-level testing includes a semiconductor die having at least one die contact electrically exposed for coupling with a redistribution circuit that electrically couples at least one die contact to an extended contact such as a bumped contact. A wafer-level redistribution circuit interconnects a plurality of dice and includes a redistribution circuit for coupling between a die contact on one of the dice and a corresponding bumped contact. The wafer-level redistribution circuit further includes a bus conductor traversing each of the plurality of dice for electrically coupling with at least another one of the plurality of dice. At least one other conductor couples the redistribution circuit to the bus conductor.

Abstract: A method of fabricating a substrate is disclosed. Apertures are formed in a substrate blank. A conductive layer is formed on opposing surfaces of the substrate, as well as inside the apertures. Conductive elements are defined on one or both opposing surfaces by masking and etching. Additional layers of conductive materials may be used to provide a barrier layer and a noble metal cap for the conductive elements. The methods of the present invention may be used to fabricate an interposer for use in packaging semiconductor devices or a test substrate. Substrate precursor structures are also disclosed.

Abstract: The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the invention includes methods in which one or more processing steps associated with fabrication and patterning of bond pads and redistribution layers is conducted simultaneously over a fuse box region to form and/or remove materials that are directly over the fuse box region.

Abstract: Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed in place to form a layer lining the via. The lined via may then be filled with a desired material. For example, a via lined with an insulative material may be filled with a material such as copper to create an insulated conductive via through the substrate.

Abstract: Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed in place to form a layer lining the via. The lined via may then be filled with a desired material. For example, a via lined with an insulative material may be filled with a material such as copper to create an insulated conductive via through the substrate.

Abstract: Methods for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed in place to form a layer lining the via. The lined via may then be filled with a desired material. For example, a via lined with an insulative material may be filled with a material such as copper to create an insulated conductive via through the substrate.

Abstract: A semiconductor component configured for wafer-level testing includes a semiconductor die having at least one die contact electrically exposed for coupling with a redistribution circuit that electrically couples at least one die contact to an extended contact such as a bumped contact. The component further includes a bus conductor that traverses at least a portion of the die and electrically mates with corresponding bus conductors on other similarly prepared components on the wafer. Functional and nonfunctional dice are identified on the wafer and the nonfunctional dice are isolated from the wafer-level testing grid. Following test, dice may be subsequently tested or moved to singulation wherein the die-to-die interconnection is interrupted, allowing wafer-level tested components to be conventionally assembled.

Abstract: The use of a resist latent image alignment mark in lieu of using dedicated discrete alignment targets defined on a semiconductor wafer and the use of field oxide step heights for alignment during the fabrication of circuit devices are disclosed. A resist latent image alignment mark is formed in a layer of photoresist material and utilized to position a mask for exposing portions of the photoresist to a radiation source to pattern locations for active areas on a semiconductor substrate. A LOCOS isolation structure is then formed around the active areas. The isolation structure is formed such that the depth of the isolation structure is adjusted to a particular radiation source wavelength. The depth of the isolation structure can then be used as a diffraction grating for stepper alignment. Isolation structure height may also be used as a diffraction grating for stepper alignment.

Abstract: A semiconductor component configured for wafer-level testing includes a semiconductor die having at least one die contact electrically exposed for coupling with a redistribution circuit that electrically couples at least one die contact to an extended contact such as a bumped contact. The component further includes a bus conductor that traverses at least a portion of the die and electrically mates with corresponding bus conductors on other similarly prepared components on the wafer. Functional and nonfunctional dice are identified on the wafer and the nonfunctional dice are isolated from the wafer-level testing grid. Following test, dice may be subsequently tested or moved to singulation wherein the die-to-die interconnection is interrupted, allowing wafer-level tested components to be conventionally assembled.

Abstract: A semiconductor component configured for wafer-level testing includes a semiconductor die having at least one die contact electrically exposed for coupling with a redistribution circuit that electrically couples at least one die contact to an extended contact such as a bumped contact. The component further includes a bus conductor that traverses at least a portion of the die and electrically mates with corresponding bus conductors on other similarly prepared components on the wafer. Functional and nonfunctional dice are identified on the wafer and the nonfunctional dice are isolated from the wafer-level testing grid. Following test, dice may be subsequently tested or moved to singulation wherein the die-to-die interconnection is interrupted, allowing wafer-level tested components to be conventionally assembled.

Abstract: Methods for creating lined vias in semiconductor substrates. Using electrophoretic techniques deposit, micelles of a lining material are deposited on the walls of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed in place to form a layer lining the via. The lined via may then be filled with a desired material. For example a via lined with an insulative material may be filled with a material such as copper to create a insulated conductive via through the substrate.

Abstract: The use of a resist latent image alignment mark in lieu of using dedicated discrete alignment targets defined on a semiconductor wafer and the use of field oxide step heights for alignment during the fabrication of circuit devices are disclosed. A resist latent image alignment mark is formed in a layer of photoresist material and utilized to position a mask for exposing portions of the photoresist to a radiation source to pattern locations for active areas on a semiconductor substrate. A LOCOS isolation structure is then formed around the active areas. The isolation structure is formed such that the depth of the isolation structure is adjusted to a particular radiation source wavelength. The depth of the isolation structure can then be used as a diffraction grating for stepper alignment. Isolation structure height may also be used as a diffraction grating for stepper alignment.

Abstract: A semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, a) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein; and b) while fabricating integrated circuitry elsewhere on the wafer, processing a first portion of at least one of the alignment patterns differently from a second portion of the one alignment pattern to render the first portion to be different from the second portion in the one alignment pattern. Such preferably superimposes a secondary step, most preferably of the same degree, over only a portion of the elevation steps in at least one of the wafer alignment patterns.

Abstract: A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. Another method of forming the stack includes forming a pad oxide layer on the semiconductor substrate assembly. A first oxidation diffusion barrier layer is then formed on the pad oxide layer, an inorganic antireflective material layer is formed on the first oxidation diffusion barrier layer, and a second oxidation diffusion barrier layer is formed on the inorganic antireflective material layer.

Abstract: The use of a resist latent image alignment mark in lieu of using dedicated discrete alignment targets defined on a semiconductor wafer and the use of field oxide step heights for alignment during the fabrication of circuit devices are disclosed. A resist latent image alignment mark is formed in a layer of photoresist material and utilized to position a mask for exposing portions of the photoresist to a radiation source to pattern locations for active areas on a semiconductor substrate. A LOCOS isolation structure is then formed around the active areas. The isolation structure is formed such that the depth of the isolation structure is adjusted to a particular radiation source wavelength. The depth of the isolation structure can then be used as a diffraction grating for stepper alignment. Isolation structure height may also be used as a diffraction grating for stepper alignment.