Abstract: A friction clutch is provided that includes a clutch cover, an intermediate plate that is spaced apart from an engine flywheel, a first friction disk positioned between the flywheel and the intermediate plate, a pressure plate spaced apart from the intermediate plate and a second friction disk positioned between the intermediate plate and the pressure plate. The clutch further includes a first drive strap for applying a load to the intermediate plate, a second drive strap for applying a load to the pressure plate and a separator arm attached to the intermediate plate. The separator arm engages the second drive strap such that axial movement of the intermediate plate relative to the clutch cover is a fraction of the corresponding axial movement of the pressure plate during engagement and disengagement of the clutch.

Abstract: A memory having built-in self repair with column shifting is provided. The total single columns are divided into smaller column groups and a bad column group is repaired with a redundant column group. Each column group is multiplexed into a pair of column group bitlines, which are fed into a shift circuit for the column group and a shift circuit for an adjacent column group. The shift circuit for the column group nearest the redundant column group receives the bitlines for that column group and the redundant column group bitlines. If a bad column group is detected, then starting with the column group furthest from the redundant column group, the shift circuit for each column group before the bad column group is deactivated. The shift circuit for the bad column group and the shift circuit for each column group after the bad column group are activated. Therefore, the bad column group is shifted out of the memory and the redundant column group fills the void.

Abstract: A method for changing the internal timing of a memory to allow adjustment of the access time of the memory to be faster or slower by increasing or decreasing internal margins of the memory (bit line separation), respectively, utilizes the memory compiler for setting the number of core cells used for driving a self time column of the memory.

Abstract: A tri-state sense amplifier is provided, which includes an enable input, a latch and an output driver. The latch has first and second complementary inputs and first and second complementary latch outputs, which are gated by the enable input. The output driver includes a data output, a pull-up transistor coupled to the data output and having a control terminal coupled to the first latch output, and a pull-down transistor coupled to the data output and having a control terminal coupled to the second latch output.

Abstract: A friction clutch is provided that includes a clutch cover, an intermediate plate that is spaced apart from an engine flywheel, a first friction disk positioned between the flywheel and the intermediate plate, a pressure plate spaced apart from the intermediate plate and a second friction disk positioned between the intermediate plate and the pressure plate. The clutch further includes a first drive strap for applying a load to the intermediate plate, a second drive strap for applying a load to the pressure plate and a separator arm attached to the intermediate plate. The separator arm engages the second drive strap such that axial movement of the intermediate plate relative to the clutch cover is a fraction of the corresponding axial movement of the pressure plate during engagement and disengagement of the clutch.

Abstract: A method for changing the internal timing of a memory to allow adjustment of the access time of the memory to be faster or slower by increasing or decreasing internal margins of the memory (bit line separation), respectively, utilizes the memory compiler for setting the number of core cells used for driving a self time column of the memory.

Abstract: A method of forming a memory cell according to the present invention. A first pass gate transistor is formed of a first transistor type. The first pass gate transistor has a gate oxide with a first thickness. The source of the first pass gate transistor is electrically connected to a first bit line, and the drain of the first pass gate transistor is electrically connected to a first state node. The gate of the first pass gate transistor is electrically connected to a memory cell enable line. A second pass gate transistor is also formed of the first transistor type. The second pass gate transistor also has a gate oxide with the first thickness. The source of the second pass gate transistor is electrically connected to a second bit line, and the drain of the second pass gate transistor is electrically connected to a second state node. The gate of the second pass gate transistor is electrically connected to the memory cell enable line. A first state node transistor is also formed of the first transistor type.