Abstract: Lines are fabricated by patterning a hard mask to provide a line segment, the line segment having a first dimension measured across the line segment; reacting a surface layer of the line segment to form a layer of a reaction product on a remaining portion of the line segment; and removing the reaction product without attacking the remaining portion of the line segment and without attacking the substrate to form the line segment with a dimension across the line segment that is smaller than the first dimension.

Abstract: A method and system for applying run rules on an individual part number basis in order to detect out-of-control events for a distinct sub-population within a general technology population. The invention thus provides for line tailoring by part number by acquiring measurement data of the part number from a manufacturing line for a measured parameter; retrieving a specification for the part number from a database; executing custom run rules by part number against the measured data using the specifications; and rejecting requests to process the part number if a run rule violation exists.

Abstract: A method and system for applying run rules on an individual part number basis in order to detect out-of-control events for a distinct sub-population within a general technology population. The invention thus provides for line tailoring by part number by acquiring measurement data of the part number from a manufacturing line for a measured parameter; retrieving a specification for the part number from a database; executing custom run rules by part number against the measured data using the specifications; and rejecting requests to process the part number if a run rule violation exists.

Abstract: The present invention discloses the use of ion implant recipe changes to control the effective channel length by compensating for any variation in the gate electrode width. The invention provides a method for controlling the effective channel length in FETs by measuring the gate electrode width, sending the measured gate electrode width to an ion implant controller, calculating a desired ion implant condition which compensates for any deviation in the effective channel length from target, and subsequently selecting or generating an ion implant recipe based on the desired conditions. Such ion implant recipe is then implanted into the FET to control the effective channel length by defining the halo, LDD, source, drain, or any other doped regions of the device which define the effective channel length, thereby resulting in a manufacturing process with higher yields and less scrap.

Abstract: The present invention discloses the use of ion implant recipe changes to control the effective channel length by compensating for any variation in the gate electrode width. The invention provides a method for controlling the effective channel length in FETs by measuring the gate electrode width, sending the measured gate electrode width to an ion implant controller, calculating a desired ion implant condition which compensates for any deviation in the effective channel length from target, and subsequently selecting or generating an ion implant recipe based on the desired conditions. Such ion implant recipe is then implanted into the FET to control the effective channel length by defining the halo, LDD, source, drain, or any other doped regions of the device which define the effective channel length, thereby resulting in a manufacturing process with higher yields and less scrap.

Abstract: The present invention discloses the use of ion implant recipe changes to control the effective channel length by compensating for any variation in the gate electrode width. The invention provides a method for controlling the effective channel length in FETs by measuring the gate electrode width, sending the measured gate electrode width to an ion implant controller, calculating a desired ion implant condition which compensates for any deviation in the effective channel length from target, and subsequently selecting or generating an ion implant recipe based on the desired conditions. Such ion implant recipe is then implanted into the FET to control the effective channel length by defining the halo, LDD, source, drain, or any other doped regions of the device which define the effective channel length, thereby resulting in a manufacturing process with higher yields and less scrap.

Abstract: The present invention discloses the use of ion implant recipe changes to control the effective channel length by compensating for any variation in the gate electrode width. The invention provides a method for controlling the effective channel length in FETs by measuring the gate electrode width, sending the measured gate electrode width to an ion implant controller, calculating a desired ion implant condition which compensates for any deviation in the effective channel length from target, and subsequently selecting or generating an ion implant recipe based on the desired conditions. Such ion implant recipe is then implanted into the FET to control the effective channel length by defining the halo, LDD, source, drain, or any other doped regions of the device which define the effective channel length, thereby resulting in a manufacturing process with higher yields and less scrap.

Abstract: Lines are fabricated by patterning a hard mask to provide a line segment, the line segment having a first dimension measured across the line segment; reacting a surface layer of the line segment to form a layer of a reaction product on a remaining portion of the line segment; and removing the reaction product without attacking the remaining portion of the line segment and without attacking the substrate to form the line segment with a dimension across the line segment that is smaller than the first dimension.

Abstract: A computer is used for generating a part inspection plan for a coordinate measuring machine (CMM), in a feature-based rapid design system (RDS), having a Feature-Based Design Environment (FBDE), an Episodal Associative Memory (EAM), Fabrication Planning (FAB), and an Inspection Plan (INSP), with features which include form features (D1) which define the form or shape of the part, manufacturing features (D2), inspection features (D3), and geometric and design (GD&T) features (D4). The Inspection Plan (INSP) includes interaction means wherein the inspector interacts with the system to guide it to a desired result, and the inspector can define setups, measurement points, sequence for the points, and the via points.