Abstract: In some embodiments, the invention includes system comprising a circuit board including a circuit board trace. This system includes a packaged chip supported by the circuit board including, the packaged chip having a package, wherein the circuit board trace is connected to the package in a circuit board breakout region, and wherein the circuit board trace includes a fan-out trace section having an impedance Zo1, a matching region trace section having an impedance Zo2, and a package trace compensation section having an impedance Zo3, wherein an effective impedance of the matching region trace section and the package trace compensation section is approximately equal to impedance Zo1, where Zo3<Zo1<Zo2.

Abstract: In some embodiments, the invention includes system comprising a circuit board including a circuit board trace. This system includes a packaged chip supported by the circuit board including, the packaged chip having a package, wherein the circuit board trace is connected to the package in a circuit board breakout region, and wherein the circuit board trace includes a fan-out trace section having an impedance Zo1, a matching region trace section having an impedance Zo2, and a package trace compensation section having an impedance Zo3, wherein an effective impedance of the matching region trace section and the package trace compensation section is approximately equal to impedance Zo1, where Zo3<Zo1<Zo2.

Abstract: A method and apparatus for a selectable RON driver impedance is described. The method includes the detection of a system memory configuration within a memory channel coupled to a chipset driver/receiver. Once the system memory configuration is detected, a driver output impedance of the chipset driver is set according to the detected system memory configuration. As a result, by dynamically setting the driver output impedance according to the detected system memory configuration, voltage swings, as well as reflections, along the memory bus transmission lines are avoided. Consequently, the amount of time required for a signal to propagate along a memory bus from the chipset driver to the actual memory device is effectively reduced and thereby increases a total interconnect timing budget.