Patents by Inventor Steven M. Thurber

Steven M. Thurber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7380046
    Abstract: A computer-implemented method, apparatus, and computer program product are disclosed in a data processing environment that includes host computer systems that are coupled to adapters utilizing a switched fabric for routing packets between the host computer systems and the adapters. A unique destination identifier is assigned to one of the host computer systems. A portion of a standard format packet destination address is selected. Within a particular packet, the portion is set equal to the unique identifier that is assigned to the host computer system. The particular packet is then routed through the fabric to the host computer system using the unique destination identifier.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: May 27, 2008
    Assignee: International Business Machines Corporation
    Inventors: William T. Boyd, Douglas M. Freimuth, William G. Holland, Steven W. Hunter, Renato J. Recio, Steven M. Thurber, Madeline Vega
  • Publication number: 20080109564
    Abstract: A message signaled interrupt (MSI) specifying an input/output (I/O) address in I/O address space is received. In response to receipt of the MSI, a translation data structure is accessed and the I/O address is translated into a physical memory address by reference to the translation data structure. The MSI is then enqueued in an event queue at the physical memory address for subsequent servicing.
    Type: Application
    Filed: November 3, 2006
    Publication date: May 8, 2008
    Inventors: Richard L. Arndt, Steven M. Thurber, Maneesh Sharma
  • Patent number: 7363404
    Abstract: System and method for managing routing of data in a distributed computing system, such as a distributed computing system that uses PCI Express protocol to communicate over an I/O fabric. A physical tree that is indicative of a physical configuration of the distributed computing system is determined, and a virtual tree is created from the physical tree. The virtual tree is then modified to change an association between at least one source device and at least one target device in the virtual tree. A validation mechanism validates the changed association between the at least one source device and the at least one target device to enable routing of data from the at least one source device to the at least one target device.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: April 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: William T. Boyd, Douglas M. Freimuth, William G. Holland, Steven W. Hunter, Renato J. Recio, Steven M. Thurber, Madeline Vega
  • Publication number: 20080092148
    Abstract: An apparatus and method for splitting responsibilities for communicating with an endpoint between a device driver and device driver services are provided. With the apparatus and method, the device driver is responsible for managing queues for communicating requests between applications in a logical partition and the endpoint. The device driver further invokes memory management via device driver services. The device driver services are responsible for managing memory accessible by the endpoint, including the address translation and protection table (ATPT) or a root complex and the address translation caches (ATCs) of the endpoint. The device driver services may associate untranslated addresses for data structures used to communicate between a system image and the endpoint. The endpoint may request translations of the untranslated addresses and may cache the translations in the ATCs.
    Type: Application
    Filed: October 17, 2006
    Publication date: April 17, 2008
    Inventors: Daniel F. Moertl, Renato J. Recio, Claudia A. Salzberg, Steven M. Thurber
  • Publication number: 20080091915
    Abstract: An apparatus and method for communicating with a memory registration enabled adapter, such as an InfiniBand™ host channel adapter, are provided. With the apparatus and method, device driver services may be invoked by a device driver for initializing address translation entries in an address translation data structure of a root complex. An address of a device driver data buffer data structure and registration modifiers may be passed by the device driver to the device driver services. The device driver services may create address translation data structure entries in the address translation data structure associated with the root complex and memory registration (MR) address translation entries in a MR address translation data structure of the adapter. The MR address translation data structure may then be used with I/O operations to bypass the address translation data structure associated with the root complex.
    Type: Application
    Filed: October 17, 2006
    Publication date: April 17, 2008
    Inventors: Daniel F. Moertl, Renato J. Recio, Claudia A. Salzberg, Steven M. Thurber
  • Publication number: 20080091855
    Abstract: An apparatus and method for communicating with an input/output (I/O) adapter configured to communicate with a locally attached I/O device are provided using cached address translations. With the apparatus and method, in response to receiving a storage transaction request, a queue element is created in a command queue specifying an untranslated buffer address. The queue element may be retrieved by the I/O adapter and a determination may be made as to whether the queue element contains a read operation command. If so, a translation request may be sent from the I/O adapter to a root complex at substantially a same time as the read operation command is sent to a locally attached external I/O device. The translated address corresponding to the untranslated address of the queue element may be returned and stored in the I/O adapter prior to receiving the data read from the external I/O device.
    Type: Application
    Filed: October 17, 2006
    Publication date: April 17, 2008
    Inventors: Daniel F. Moertl, Renato J. Recio, Claudia A. Salzberg, Steven M. Thurber
  • Patent number: 5694556
    Abstract: A data processing system includes a host processor, a number of peripheral devices, and one or more bridges which may connect between the host, peripheral devices and other hosts or peripheral devices such as in a network. Each bus to bus bridge connects between a primary bus and a secondary bus wherein for the purpose of clarity, the primary bus will be considered as the source for outbound transactions and the destination for inbound transactions and the secondary bus would be considered the destination for outbound transactions and the source for inbound transactions. Each bus to bus bridge includes an outbound data path, an inbound data path, and a control mechanism. The outbound data path includes a queued buffer for storing transactions in order of receipt from the primary bus where the requests in the queued buffer may be mixed as between read requests and write transactions, the outbound path also includes a number of parallel buffers for storing read reply data and address information.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 2, 1997
    Assignee: International Business Machines Corporation
    Inventors: Dan M. Neal, Edward J. Silha, Steven M. Thurber
  • Patent number: 5548735
    Abstract: A system and method for asynchronously managing the issuance of program I/O store instructions from a high speed central processor to a multiplicity of relatively lower speed I/O adapter devices. An interface between the central processor and the I/O adapter devices includes a program I/O store queue, a state machine, and a token pool related in count to the concurrent processing capabilities of I/O controllers. The interface queue includes information for uniquely identifying program I/O store instructions by adapter device destination and user application program to manage error recovery. As preferably implemented, the interface system and method also distinctly manages program I/O instructions requiring synchronous execution, such as program I/O load instructions.
    Type: Grant
    Filed: September 15, 1993
    Date of Patent: August 20, 1996
    Assignee: International Business Machines Corporation
    Inventors: Wen-Tzer T. Chen, Steven M. Thurber, Gary Y. Tsao