Abstract: Load switch supply circuits and methods are provided that allow a load switch to maintain power delivery without having the load switch encounter thermal or power overload conditions. In an example, a load switch supply circuit can include a multiplier circuit configured to receive a first representation of voltage across a load switch and a representation of current provided by the load switch and to provide a representation of power dissipated by the load switch, and a control amplifier configured to compare the representation of power dissipated by the load switch to a power threshold and to adjust a control terminal of the load switch to avoid cycling the load switch to an off state due to thermal overload or power overload conditions.

Abstract: A switch can be configured to receive a first signal at a first input and provide an output signal at an output, depending on a state of the switch. A switch state change can be delayed until an indication of a requested switch state different than a current switch state is received and the first signal reaches a threshold.

Abstract: This document discusses, among other things, apparatus and methods including an analog-to-digital controller (ADC) configured to receive an enable signal and to provide an ADC output signal to control logic, wherein the control logic is configured to provide a control voltage to a control input of a switch. In an example, the control voltage includes the ADC output signal when the ADC output signal is below a first threshold or above a second threshold. In certain examples, the control logic is configured to transition the control voltage from the first threshold to the second threshold when the ADC output signal is between the first and second thresholds.

Abstract: This document discloses, among other things, a voltage clamp circuit where an output voltage equals an input voltage for at least a portion of a first range of input voltages, and where the output voltage is less than the input voltage for at least a portion of a second range of input voltages.

Abstract: A switch can be configured to receive a first signal at a first input and provide an output signal at an output, depending on a state of the switch. A switch state change can be delayed until an indication of a requested switch state different than a current switch state is received and the first signal reaches a threshold.

Abstract: A switch can be configured to receive a first signal at a first input and provide an output signal at an output, depending on a state of the switch. A switch state change can be delayed until an indication of a requested switch state different than a current switch state is received and the first signal reaches a threshold.

Abstract: This document discloses, among other things, a voltage clamp circuit where an output voltage equals an input voltage for at least a portion of a first range of input voltages, and where the output voltage is less than the input voltage for at least a portion of a second range of input voltages.

Abstract: This document discusses, among other things, apparatus and methods including an analog-to-digital controller (ADC) configured to receive an enable signal and to provide an ADC output signal to control logic, wherein the control logic is configured to provide a control voltage to a control input of a switch. In an example, the control voltage includes the ADC output signal when the ADC output signal is below a first threshold or above a second threshold. In certain examples, the control logic is configured to transition the control voltage from the first threshold to the second threshold when the ADC output signal is between the first and second thresholds.

Abstract: This document discusses, among other things, apparatus and methods for passing a signal in a power down state. An example switch device can include a first depletion-mode transistor configured to pass an analog signal between a first node and a second node in a first state and to isolate the first node from the second node in a second state, a control circuit coupled to a control node of the first depletion-mode transistor and configured to isolate the control node from a first supply input in the first state and to couple the control node to the first supply input in the second state, and a tracking circuit configured to couple the control node of the first depletion-mode transistor to the first node during the first state and to isolate the control node of the first depletion-mode transistor from the first node in the second state.

Abstract: This document discusses, among other things, a compensation circuit configured to modulate a control voltage of a switch over a range of ambient temperatures during a conduction state of the switch to maintain a specified resistance between first and second nodes of the switch. The compensation circuit can include a temperature-insensitive resistor configured to provide a sense current, a current mirror configured to provide a mirror current using the sense current, and a temperature-sensitive resistor configured to provide the control voltage using the mirror current.

Abstract: This application discusses, among other things, switch circuit apparatus having power down protection and not requiring power up sequencing. An apparatus embodiment can include a first supply node coupled to a first input of a level shifting circuit via a protection circuit, a second supply node coupled to a second input of the level shifting circuit via a single pull-up transistor, and a switch including a control input, a first node, and a second node controllably isolated from the first node, wherein the control input is coupled to the level shifting circuit. The first and second inputs of the level shifting circuit can be coupled via a rectifier, and the protection circuit can be configured to power the first and second supply nodes to controllably isolate the first and second nodes from each other when a voltage of one of the first or second nodes exceeds a threshold.

Abstract: This document discusses, among other things, apparatus and methods for passing a signal in a power down state. An example switch device can include a first depletion-mode transistor configured to pass an analog signal between a first node and a second node in a first state and to isolate the first node from the second node in a second state, a control circuit coupled to a control node of the first depletion-mode transistor and configured to isolate the control node from a first supply input in the first state and to couple the control node to the first supply input in the second state, and a tracking circuit configured to couple the control node of the first depletion-mode transistor to the first node during the first state and to isolate the control node of the first depletion-mode transistor from the first node in the second state.

Abstract: This document discusses, among other things, a compensation circuit configured to modulate a control voltage of a switch over a range of ambient temperatures during a conduction state of the switch to maintain a specified resistance between first and second nodes of the switch. The compensation circuit can include a temperature-insensitive resistor configured to provide a sense current, a current mirror configured to provide a mirror current using the sense current, and a temperature-sensitive resistor configured to provide the control voltage using the mirror current.

Abstract: A system and process for eliminating a control wire between logic systems that communicate with each other. In one embodiment, a system sends to a receiver a frequency that indicates a first mode. In the first mode a first data type may be sent. When the frequency is changed a second mode is indicated wherein a second data type may be sent. The receiver detects the frequency change and assumes the first or second mode as indicated.

Abstract: This application discusses, among other things, switch circuit apparatus having power down protection and not requiring power up sequencing. An apparatus embodiment can include a first supply node coupled to a first input of a level shifting circuit via a protection circuit, a second supply node coupled to a second input of the level shifting circuit via a single pull-up transistor, and a switch including a control input, a first node, and a second node controllably isolated from the first node, wherein the control input is coupled to the level shifting circuit. The first and second inputs of the level shifting circuit can be coupled via a rectifier, and the protection circuit can be configured to power the first and second supply nodes to controllably isolate the first and second nodes from each other when a voltage of one of the first or second nodes exceeds a threshold.

Abstract: A switch can be configured to receive a first signal at a first input and provide an output signal at an output, depending on a state of the switch. A switch state change can be delayed until an indication of a requested switch state different than a current switch state is received and the first signal reaches a threshold.

Abstract: A system and process for eliminating a control wire between logic systems that communicate with each other. In one embodiment, a system sends to a receiver a frequency that indicates a first mode. In the first mode a first data type may be sent. When the frequency is changed a second mode is indicated wherein a second data type may be sent. The receiver detects the frequency change and assumes the first or second mode as indicated.

Abstract: Box switches are stacked sharing a common current from power sources. The power sources may be current, voltage or a combination of such sources. In preferred embodiments, the transistor switches in the box switches may be paralleled by different polarity transistors that will act to better balance and make symmetrical the output signals. Capacitors may be used to smooth out residual noise voltage signals.

Abstract: An enveloping curves generator is disclosed that guarantees that one curve will envelop or overlap another when both are traversing from one logic level to another, and where the other overlaps the first when both traversing the other direction. In one case, a steering FET controlled by an input signal drives a first output high via a circuit. That first output going high, after a delay, drives a second output high. When the input goes low, a second steering FET controlled by the input signal drives the second output low. That second output going low, after a delay, drives the first output low. No latching is provided in the present invention.

Abstract: A differential transmission line driver with supplemental current sources that overcome switching anomalies and EMU issues when the logic state of the driver is switching. During a logic transition, a current source, that is directed to the output of the driver, may be prevented from delivering its current. The present invention provides a supplemental current that is active during this transition period to supply the missing current. The present disclosure also details a common mode circuit that maintains a stable common mode output level to help control EMI issues when the power supply for the driver changes.