Abstract: Provided is a method for securing against side channel attacks. An elliptic curve cryptographic process comprises a multiple points multiplication operation using predetermined scalar values, Pi being points of an elliptic curve over a finite field defined by parameters (F, E, G, N) together with the point addition law where F is a field over which is defined the curve, E is an equation of the curve, G is a base point in E over F and N is the order of the base point G. The method comprises generating (S1) a masking value iRand, multiplicatively masking (S2) each predetermined scalar value di with said generated masking value iRand to obtain masked scalars di?, computing (S3) a masked multiple points multiplication operation result, and obtaining (S4) said multiple points multiplication operation result R by unmasking said masked multiple points multiplication operation result R?.

Abstract: The present invention relates to a computing device for executing a first cryptographic operation of a cryptographic process on useful input data, said computing device comprising a first processor, a second processor and a selection circuit wherein: —said selection circuit is configured: —for receiving, from an input bus, expanded input data obtained by interleaving dummy input data with said useful input data, —for determining positions of the dummy input data in said expanded input data, —and for extracting said dummy input data and said useful input data from the expanded input data based on said determined positions, —said first processor is configured for executing said first cryptographic operation of said cryptographic process on said extracted useful input data to obtain useful output data, —said second processor is configured for executing a second operation on said extracted dummy input data to obtain dummy output data, said computing device being configured for having said operations executed such

Abstract: The present invention relates to a computing device for executing a first cryptographic operation of a cryptographic process on useful input data, said computing device comprising a first processor, a second processor and a selection circuit wherein: said selection circuit is configured: for receiving, from an input bus, expanded input data obtained by interleaving dummy input data with said useful input data, for determining positions of the dummy input data in said expanded input data, and for extracting said dummy input data and said useful input data from the expanded input data based on said determined positions, said first processor is configured for executing said first cryptographic operation of said cryptographic process on said extracted useful input data to obtain useful output data, said second processor is configured for executing a second operation on said extracted dummy input data to obtain dummy output data, said computing device being configured for having said operations executed such that