Abstract: Data processing and an accelerator system therefor are described. An embodiment relates generally to a data processing system. In such an embodiment, a bus and an accelerator are coupled to one another. The accelerator has an application function block. The application function block is to process data to provide processed data to storage. A network interface is coupled to obtain the processed data from the storage for transmission.

Abstract: Data processing and an accelerator system therefore are described. An embodiment relates generally to a data processing system. In such an embodiment, a bus and an accelerator are coupled to one another. The accelerator has an application function block. The application function block is to process data to provide processed data to storage. A network interface is coupled to obtain the processed data from the storage for transmission.

Abstract: In an embodiment, a plurality of memory dies is coupled as a memory block. The memory block has an access width defined as a system word length divided by a burst length associated with the plurality of memory dies. The burst length is greater than one. A single word having the system word length is written or read in a write operation or a read operation, respectively, through a write burst or a read burst, respectively, for random access memory operation with a granularity of the single word.

Abstract: A compiler and language using the comma as a parallelism operator may ensure that variables on the left hand side of a line of code are only used once, and that the variables on the left hand side of the line of code are not being used as function arguments. Commas may be replaced with semi-colons.

Abstract: Data processing and an accelerator system therefor are described. An embodiment relates generally to a data processing system. In such an embodiment, a bus and an accelerator are coupled to one another. The accelerator has an application function block. The application function block is to process data to provide processed data to storage. A network interface is coupled to obtain the processed data from the storage for transmission.

Abstract: Data processing and an accelerator system therefore are described. An embodiment relates generally to a data processing system. In such an embodiment, a bus and an accelerator are coupled to one another. The accelerator has an application function block. The application function block is to process data to provide processed data to storage. A network interface is coupled to obtain the processed data from the storage for transmission.

Abstract: Data processing and an accelerator system therefore are described. An embodiment relates generally to a data processing system. In such an embodiment, a bus and an accelerator are coupled to one another. The accelerator has an application function block. The application function block is to process data to provide processed data to storage. A network interface is coupled to obtain the processed data from the storage for transmission.

Abstract: Reconfiguration of an accelerator module having a programmable logic device is described, where the reconfiguration is performed during runtime without rebooting. For example, a computer is put into a sleep mode, the computer having the accelerator module installed therein. A programmable logic device of the accelerator module is reconfigured while the computer is in the sleep mode.

Abstract: Data processing and an accelerator system therefore are described. An embodiment relates generally to a data processing system. In such an embodiment, a bus and an accelerator are coupled to one another. The accelerator has an application function block. The application function block is to process data to provide processed data to storage. A network interface is coupled to obtain the processed data from the storage for transmission.

Abstract: Data processing and an accelerator system therefor are described. An embodiment relates generally to a data processing system. In such an embodiment, a bus and an accelerator are coupled to one another. The accelerator has an application function block. The application function block is to process data to provide processed data to storage. A network interface is coupled to obtain the processed data from the storage for transmission.

Abstract: An array of FPGAs change their configurations successively during performance of successive user-defined algorithms. Adjacent FPGAs are connected through external field programmable interconnection devices (FPINs) or cross-bar switches. The array includes a processor-like device capable of performing the computations necessary to reconfigure the FPGAs in the array in accordance with the next algorithm to be performed. Preferably, this processor-like device is itself a "control" array of interconnected FPGAs which have been configured to emulate a selected microprocessor architecture which accepts user-defined primitives corresponding to an algorithm to be performed or a logic architecture to be emulated and reconfigure the FPGAs and the FPINs accordingly.