Abstract: A method and circuit for providing a bias voltage to a MOS device is disclosed. The method and circuit comprise utilizing at least one diode connected circuit to provide a voltage that tracks process, voltage and temperature variations of a semiconductor device. The method and circuit includes utilizing a current mirror circuit coupled to the at least one diode connected circuit to generate a bias voltage for the body of the semiconductor device from the voltage. The bias voltage allows for compensation for the process, voltage and temperature variations.

Abstract: A clock signal duty cycle adjustment circuit includes a duty cycle correction circuit that receives a clock input signal that may need duty cycle correction. The duty cycle correction circuit may derive first and second differential clock signals from the clock input signal. The first and second differential clock signals may exhibit respective voltage offsets. The duty cycle correction circuit includes a voltage offset shift circuit that may shift the voltage offset that one of the first and second differential clock signals exhibits to adjust the effective duty cycle of a clock output signal. The duty cycle adjustment circuit derives the clock output signal from the voltage offset adjusted first and second differential clock signals in response to a duty cycle error signal.

Abstract: A clock signal duty cycle adjustment circuit includes a duty cycle correction circuit that receives a clock input signal that may need duty cycle correction. The duty cycle correction circuit may derive first and second differential clock signals from the clock input signal. The first and second differential clock signals may exhibit respective voltage offsets. The duty cycle correction circuit includes a voltage offset shift circuit that may shift the voltage offset that one of the first and second differential clock signals exhibits to adjust the effective duty cycle of a clock output signal. The duty cycle adjustment circuit derives the clock output signal from the voltage offset adjusted first and second differential clock signals in response to a duty cycle error signal.

Abstract: A method and circuit for providing a bias voltage to a MOS device is disclosed. The method and circuit comprise utilizing at least one diode connected circuit to provide a voltage that tracks process, voltage and temperature variations of a semiconductor device. The method and circuit includes utilizing a current mirror circuit coupled to the at least one diode connected circuit to generate a bias voltage for the body of the semiconductor device from the voltage. The bias voltage allows for compensation for the process, voltage and temperature variations.

Abstract: A system is disclosed. The system includes a first circuit, the first circuit includes a bias device for allowing the first circuit to transition between a first mode and a second mode. The system further includes a second circuit which controls the bias device. The second circuit provides a bias voltage at a sub-threshold voltage level to the bias device when the first device is in one of the first and the second mode. The second circuit provides a bias voltage at a threshold voltage level or higher when the first device is in one of the first and the second mode. Accordingly, the transition time between modes of the first circuit is minimized.