Patents by Inventor Steven McLaughlin

Steven McLaughlin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11957875
    Abstract: Disclosed are a device, system, methods and computer-readable medium products that provide an updated insulin-to-carbohydrate ratio and an updated total daily insulin. The described processes may be used for periodic updating of the insulin-to-carbohydrate ratio and the total daily insulin. The insulin-to-carbohydrate ratio and/or the total may be used in the calculation of new doses of insulin that a drug delivery device may be commanded to deliver to a user.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: April 16, 2024
    Assignee: INSULET CORPORATION
    Inventors: Yibin Zheng, Joon Bok Lee, Steven Cardinali, Jason O'Connor, Eric Benjamin, Ian McLaughlin, David Nazzaro, Ashutosh Zade
  • Patent number: 9959172
    Abstract: A data processing device, comprising a processing unit and a test control unit connected to the processing unit, is described. The processing unit and the test control unit are arranged to: start a logic test of the processing unit; detect a test abort event; and, in response to the test abort event, perform an event response action which comprises aborting the logic test and booting the processing unit, said booting including executing an event handling routine. The event response action may comprise setting a reset vector to an address of the event handling routine. System availability may thus be improved. In particular, the delay between capturing an asynchronous signal and responding to it may be reduced. The test abort event may, for example, be an asynchronous event having certain pre-defined characteristics. A method of operating a data processing device is also described.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: May 1, 2018
    Assignee: NXP USA, Inc.
    Inventors: Steven McLaughlin, Alan Devine, Alistair James Gorman, Alistair Paul Roberston
  • Publication number: 20170190440
    Abstract: An actively stabilized refueling drogue including a drogue canopy, drogue straits extending from the drogue canopy, a coupling body, a coupling shroud, a system of fins, and actuators. The coupling body is for connecting a flexible refueling hose to a receiver aircraft fuel intake, so that in-air refueling may occur The drogue struts terminate at the coupling body. The coupling shroud covers the coupling body. The system of fins is for stabilization of the drogue and is attached to the coupling shroud. The actuators are for actuating the fins to achieve aerodynamic stabilization. The actuators are manufactured from a solid state shape memory alloy, such that the fins may be actuated by applying thermal energy to the actuators.
    Type: Application
    Filed: January 4, 2016
    Publication date: July 6, 2017
    Applicant: United States of America as represented by the Secretary of the Navy
    Inventor: Steven McLaughlin
  • Publication number: 20160275008
    Abstract: A data processing device, comprising a processing unit and a test control unit connected to the processing unit, is described. The processing unit and the test control unit are arranged to: start a logic test of the processing unit; detect a test abort event; and, in response to the test abort event, perform an event response action which comprises aborting the logic test and booting the processing unit, said booting including executing an event handling routine. The event response action may comprise setting a reset vector to an address of the event handling routine. System availability may thus be improved. In particular, the delay between capturing an asynchronous signal and responding to it may be reduced. The test abort event may, for example, be an asynchronous event having certain pre-defined characteristics. A method of operating a data processing device is also described.
    Type: Application
    Filed: November 25, 2013
    Publication date: September 22, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Steven MCLAUGHLIN, Alan DEVINE, Alistair James GORMAN, Alistair Paul ROBERSTON
  • Patent number: 7818650
    Abstract: A channel encoding apparatus and method are provided in which part of the parity bits are set to erroneous bits, and full parity bits are created by correcting the erroneous bits using a channel decoding apparatus of a receiver in a communication system. In the channel encoding apparatus, in order to generate a coded bit stream by adding a parity bit stream to a message bit stream, a partial parity generator generates a partial parity bit stream as a part of the parity bit stream using the message bit stream, an erasure generator generates a bit stream having an erroneous value as the remaining part of the parity bit stream, and a decoder calculates the value of the parity bit stream by correcting the bit stream having the erroneous value using a parity-check matrix that determines the parity bit stream, the message bit stream, and the partial parity bit stream.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: October 19, 2010
    Assignees: Samsung Electronics Co., Ltd., Georgia Tech Research Corporation
    Inventors: Jeong-Seok Ha, Jaehong Kim, Steven McLaughlin, Seung-Bum Suh
  • Publication number: 20090031192
    Abstract: A channel encoding apparatus and method are provided in which part of the parity bits are set to erroneous bits, and full parity bits are created by correcting the erroneous bits using a channel decoding apparatus of a receiver in a communication system. In the channel encoding apparatus, in order to generate a coded bit stream by adding a parity bit stream to a message bit stream, a partial parity generator generates a partial parity bit stream as a part of the parity bit stream using the message bit stream, an erasure generator generates a bit stream having an erroneous value as the remaining part of the parity bit stream, and a decoder calculates the value of the parity bit stream by correcting the bit stream having the erroneous value using a parity-check matrix that determines the parity bit stream, the message bit stream, and the partial parity bit stream.
    Type: Application
    Filed: October 1, 2008
    Publication date: January 29, 2009
    Inventors: Jeong-Seok Ha, Jaehong Kim, Steven McLaughlin, Seung-Bum Suh
  • Patent number: 7451385
    Abstract: A channel encoding apparatus and method are provided in which part of the parity bits are set to erroneous bits, and full parity bits are created by correcting the erroneous bits using a channel decoding apparatus of a receiver in a communication system. In the channel encoding apparatus, in order to generate a coded bit stream by adding a parity bit stream to a message bit stream, a partial parity generator generates a partial parity bit stream as a part of the parity bit stream using the message bit stream, an erasure generator generates a bit stream having an erroneous value as the remaining part of the parity bit stream, and a decoder calculates the value of the parity bit stream by correcting the bit stream having the erroneous value using a parity-check matrix that determines the parity bit stream, the message bit stream, and the partial parity bit stream.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: November 11, 2008
    Assignees: Samsung Electronics Co., Ltd., Georgia Tech Research Corporation
    Inventors: Jeong-Seok Ha, Jaehong Kim, Steven McLaughlin, Seung-Bum Suh
  • Publication number: 20070226583
    Abstract: In a communication system, a signal transmission apparatus includes an encoder for encoding an information vector into a low density parity check (LDPC) codeword with an LDPC coding scheme, and a puncturer for puncturing the LDPC codeword according to a coding rate using a puncturing scheme. A signal reception apparatus includes a ‘0’ inserter for inserting ‘0’ symbols in a received signal according to a coding rate used in a signal transmission apparatus, and a decoder for decoding the ‘0’ symbol-inserted signal with a decoding scheme corresponding to a low density parity check (LDPC) coding scheme used in the signal transmission apparatus, thereby detecting an information vector.
    Type: Application
    Filed: November 22, 2006
    Publication date: September 27, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Ho Kim, Jaehong Kim, Aditya Ramamoorthy, Steven McLaughlin
  • Publication number: 20060156181
    Abstract: A method for puncturing a low density parity check (LDPC) code that is decoded through a parity check matrix expressed by a factor graph including check nodes and bit nodes connected to the check nodes through edges. The method includes classifying the bit nodes mapped to a parity part of a codeword into hierarchical groups according to their decoding facilities when the bit nodes are punctured, determining puncturing order of the groups, and sequentially performing puncturing on the bit nodes from a bit node belonging to a corresponding group according to the puncturing order of the groups to acquire a codeword with a desired coding rate.
    Type: Application
    Filed: October 27, 2005
    Publication date: July 13, 2006
    Applicants: SAMSUNG ELECTRONICS CO., LTD., GEORGIA TECH RESEARCH CORPORATION
    Inventors: Jeong-Seok Ha, Steven McLaughlin, Jaehong Kim, Seung-Bum Suh
  • Publication number: 20050216820
    Abstract: A channel encoding apparatus and method are provided in which part of the parity bits are set to erroneous bits, and full parity bits are created by correcting the erroneous bits using a channel decoding apparatus of a receiver in a communication system. In the channel encoding apparatus, in order to generate a coded bit stream by adding a parity bit stream to a message bit stream, a partial parity generator generates a partial parity bit stream as a part of the parity bit stream using the message bit stream, an erasure generator generates a bit stream having an erroneous value as the remaining part of the parity bit stream, and a decoder calculates the value of the parity bit stream by correcting the bit stream having the erroneous value using a parity-check matrix that determines the parity bit stream, the message bit stream, and the partial parity bit stream.
    Type: Application
    Filed: March 24, 2005
    Publication date: September 29, 2005
    Applicants: SAMSUNG ELECTRONICS CO., LTD., Georgia Tech Research Corporation
    Inventors: Jeong-Seok Ha, Joe-Hong Kim, Steven McLaughlin, Seung-Bum Suh
  • Publication number: 20050047044
    Abstract: A power conversion system and methods of power conversion and construction of such a system are disclosed, where the system includes at least two pairs of input and output bus bars, and two pairs of switching devices, with the switching devices of each respective pair coupled in parallel in between a respective pair of the bus bars. When one of the switching devices of each pair is closed, the bus bars of the respective pair of bus bars are short-circuited to one another, thus bypassing the other of the switching devices of each pair. The other of the switching devices of each pair is attached to at least one intermediate portion, which in turn is attached to a mass. Substantially all the heat generated by the other of the switching devices of each pair is communicated to the mass, which has a heat capacity capable of receiving that heat.
    Type: Application
    Filed: August 29, 2003
    Publication date: March 3, 2005
    Inventors: Paul Nolden, Steven McLaughlin, Matthew Alles