Patents by Inventor Steven Michnowski

Steven Michnowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ABIST-assisted detection of scan chain defects
    Patent number: 7225374
    Abstract: An apparatus, program product and method utilize an ABIST circuit provided on an integrated circuit device to assist in the identification and location of defects in a scan chain that is also provided on the integrated circuit device. In particular, a defect in a scan chain may be detected by applying a plurality of pattern sets to a scan chain coupled to an ABIST circuit, collecting scan out data generated as a result of the application of the plurality of pattern sets to the scan chain, and using the collected scan out data to identify a defective latch in the scan chain.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: May 29, 2007
    Assignee: International Business Machines Corporation
    Inventors: Todd Michael Burdine, Donato Orazio Forlenza, Orazio Pasquale Forlenza, William James Hurley, Steven Michnowski, James Bernard Webb
  • ABIST-assisted detection of scan chain defects
    Publication number: 20050138514
    Abstract: An apparatus, program product and method utilize an ABIST circuit provided on an integrated circuit device to assist in the identification and location of defects in a scan chain that is also provided on the integrated circuit device. In particular, a defect in a scan chain may be detected by applying a plurality of pattern sets to a scan chain coupled to an ABIST circuit, collecting scan out data generated as a result of the application of the plurality of pattern sets to the scan chain, and using the collected scan out data to identify a defective latch in the scan chain.
    Type: Application
    Filed: December 4, 2003
    Publication date: June 23, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Todd Burdine, Donato Forlenza, Orazio Forlenza, William Hurley, Steven Michnowski, James Webb
  • Method and system for determining repeatable yield detractors of integrated circuits
    Patent number: 6751765
    Abstract: An exemplary embodiment of the invention is a method for LBIST testing integrated circuit. The method includes generating a plurality of multi-bit test patterns and grouping the multi-bit test patterns by a plurality of test pattern partitions including a first test pattern partition having a first number of bits and a second test pattern partition having second number of bits greater than the first number. The first test pattern partition is applied to the integrated circuit to generate a first signature that is compared to a first reference signature to detect a failure. The second test pattern partition is applied to the integrated circuit to generate a second signature that is compared to a second reference signature to detect a failure in the integrated circuit.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: June 15, 2004
    Assignee: International Business Machines Corporation
    Inventors: Richard F. Rizzolo, Rocco E. DeStefano, Joseph E. Eckelman, Thomas G. Foote, Steven Michnowski, Franco Motika, Phillip J. Nigh, Bryan J. Robbins