Patents by Inventor Steven Milburn
Steven Milburn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220309134Abstract: A system including at least one processor programmed to translate a policy into policy code, wherein: the policy is provided in a policy language; the policy code is in a programming language that is different from the policy language; and the policy includes a statement that maps an entity name to one or more metadata symbols to be associated with an entity in a target system against which the policy is to be enforcedType: ApplicationFiled: April 13, 2022Publication date: September 29, 2022Applicants: Dover Microsystems, Inc., The Charles Stark Draper Laboratory, Inc.Inventors: Eli Boling, Steven Milburn, Gregory T. Sullivan, Andrew Sutherland, Christopher J. Casinghino
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Publication number: 20220300583Abstract: A system including at least one processor programmed to identify, based on a policy to be enforced, one or more metadata symbols corresponding to an entity name; identify, from a target description describing a target system, an entity description matching the entity name, wherein the entity description describes an entity of the target system; and apply a metadata label to the entity of the target system, wherein the metadata label is based on the one or more metadata symbols corresponding to the entity name, as identified based on the policy.Type: ApplicationFiled: April 1, 2022Publication date: September 22, 2022Applicant: Dover Microsystems, Inc.Inventors: Eli Boling, Steven Milburn, Gregory T. Sullivan, Andrew Sutherland
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Publication number: 20220198014Abstract: Systems and methods for violation processing. In some embodiments, in response to detecting a policy violation, tag processing hardware may enter a violation processing mode, and may cause a host processor to begin executing violation processing code. The tag processing hardware may continue checking one or more instructions in an instruction queue. In response to encountering, in the instruction queue, an instruction of the violation processing code, the tag processing hardware may exit the violation processing mode.Type: ApplicationFiled: December 23, 2021Publication date: June 23, 2022Applicant: Dover Microsystems, Inc.Inventors: Eli Boling, Steven Milburn
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Publication number: 20220129343Abstract: Systems and methods for reducing exception latency. In some embodiments, trace information regarding one or more instructions executed by a processor may be received. The trace information may indicate that the processor is entering an exception handling routine. A type of exception signal being handled by the processor may be determined based on the trace information. The type of exception signal being handled by the processor may then be used to determine whether to deactivate metadata processing. In response to determining that metadata processing is to be deactivated, state information may be updated to indicate that metadata processing is being deactivated.Type: ApplicationFiled: October 21, 2021Publication date: April 28, 2022Applicant: Dover Microsystems, Inc.Inventors: Steven Milburn, Gregory T. Sullivan
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Publication number: 20220092173Abstract: Systems and methods for metadata processing. In some embodiments, one or more metadata inputs may be processed to determine whether to allow an instruction. For instance, one or more classification bits may be identified from a metadata input of the one or more metadata inputs, and the metadata input may be processed based on the one or more classification bits.Type: ApplicationFiled: January 15, 2020Publication date: March 24, 2022Applicant: Dover Microsystems, Inc.Inventors: Andrew Sutherland, Steven Milburn, Gregory T. Sullivan, Eli Boling
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Publication number: 20220012329Abstract: Systems and methods for metadata processing. In some embodiments, a target address may be received from a host processor. The target address may be used to access mapping information and decoding information, the mapping information and the decoding information being associated with the target address. The mapping information may be used to map the target address to a metadata address. The metadata address may be used to retrieve metadata, and the decoding information may be used to decode the retrieved metadata.Type: ApplicationFiled: November 11, 2019Publication date: January 13, 2022Applicant: Dover Microsystems, Inc.Inventors: Eli Boling, Steven Milburn, Gregory T. Sullivan, Andrew Sutherland
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Publication number: 20210357497Abstract: According to at least one aspect, a hardware system include a host processor, a policy engine, and an interlock is provided. These components can interoperate to enforce security policies. The host processor can execute an instruction and provide instruction information to the policy engine and the result of the executed instruction to the interlock. The policy engine can determine whether the executed instruction is allowable according to one or more security policies using the instruction information. The interlock can buffer the result of the executed instruction until an indication is received from the policy engine that the instruction was allowable. The interlock can then release the result of the executed instruction. The policy engine can be configured to transform instructions received from the host processor or add inserted instructions to the policy evaluation pipeline to increase the flexibility of the policy engine and enable enforcement of the security policies.Type: ApplicationFiled: February 1, 2019Publication date: November 18, 2021Applicant: Dover Microsystems, Inc.Inventors: Steven Milburn, Eli Boling
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Publication number: 20210255890Abstract: Systems and methods for stalling a host processor. In some embodiments, the host processor may be caused to initiate one or more selected transactions, wherein the one or more selected transactions comprise a bus transaction. The host processor may be prevented from completing the one or more selected transactions, to thereby stall the host processor.Type: ApplicationFiled: May 5, 2021Publication date: August 19, 2021Applicant: Dover Microsystems, Inc.Inventors: Steven Milburn, Gregory T. Sullivan
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Publication number: 20210073375Abstract: According to at least one aspect, a hardware system include a host processor, a policy engine, and an interlock is provided. These components can interoperate to enforce security policies. The host processor can execute an instruction and provide instruction information to the policy engine and the result of the executed instruction to the interlock. The policy engine can determine whether the executed instruction is allowable according to one or more security policies using the instruction information. The interlock can buffer the result of the executed instruction until an indication is received from the policy engine that the instruction was allowable. The interlock can then release the result of the executed instruction. The policy engine can be configured to transform instructions received from the host processor or add inserted instructions to the policy evaluation pipeline to increase the flexibility of the policy engine and enable enforcement of the security policies.Type: ApplicationFiled: February 1, 2019Publication date: March 11, 2021Applicant: Dover Microsystems, Inc.Inventors: Steven Milburn, Eli Boling
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Publication number: 20210055954Abstract: Systems and methods for a write interlock configured to perform first processing and second processing, decoupled from the first processing. In some aspects, the first processing comprises receiving, from a processor, a store instruction including a target address, storing, in a data structure, a first entry corresponding to the store instruction, initiating a check of the store instruction against at least one policy, and in response to successful completion of the check, removing the first entry from the data structure. The second processing comprises receiving, from the processor, a write transaction including a target address, determining whether any entry in the data structure relates to the target address of the write transaction, and in response to determining that no entry in the data structure relates to the target address of the write transaction, causing the data to be written to the target address of the write transaction.Type: ApplicationFiled: February 1, 2019Publication date: February 25, 2021Applicant: Dover Microsystems, Inc.Inventors: Steven Milburn, Nirmal Nepal
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Publication number: 20210042100Abstract: A system including at least one processor programmed to translate a policy into policy code, wherein: the policy is provided in a policy language; the policy code is in a programming language that is different from the policy language; and the policy includes a statement that maps an entity name to one or more metadata symbols to be associated with an entity in a target system against which the policy is to be enforced.Type: ApplicationFiled: February 1, 2019Publication date: February 11, 2021Applicants: Dover Microsystems, Inc., The Charles Stark Draper Laboratory, Inc.Inventors: Eli Boling, Steven Milburn, Gregory T. Sullivan, Andrew Sutherland, Christopher J. Casinghino
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Publication number: 20210026934Abstract: A system including at least one processor programmed to identify, based on a policy to be enforced, one or more metadata symbols corresponding to an entity name; identify, from a target description describing a target system, an entity description matching the entity name, wherein the entity description describes an entity of the target system; and apply a metadata label to the entity of the target system, wherein the metadata label is based on the one or more metadata symbols corresponding to the entity name, as identified based on the policy.Type: ApplicationFiled: February 1, 2019Publication date: January 28, 2021Applicant: Dover Microsystems, Inc.Inventors: Eli Boling, Steven Milburn, Gregory T. Sullivan, Andrew Sutherland
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Publication number: 20060093191Abstract: A finger sensing device may include a finger sensing area to receive a user's finger moved in a sliding motion, a sensor controller cooperating with the finger sensing area for collecting image data therefrom, an image processor, and a communications path for sending image data from the sensor controller to the image processor. The sensing device may use at least one of the sensor controller and the image processor for (i) selecting a reference image data subset based upon reference image data, (ii) selecting a new image data subset, and (iii) comparing the new image data subset to the reference image data subset to develop a matching score, and, if the matching score is above a matching threshold, then not having new image data corresponding to the new image data subset sent over the data communications path, and, if the matching score is below the matching threshold, then having the new image data corresponding to the new image data subset sent over the data communications path.Type: ApplicationFiled: October 13, 2005Publication date: May 4, 2006Applicant: AuthenTec, Inc.Inventors: James Neil, Joseph Tykowski, Steven Milburn