Abstract: An input signal is mixed with sampling signals from oscillators which vary the frequency of the sampling signal from a first frequency to a second frequency. The resulting Intermediate Frequency (IF) signal is processed and digital values are stored in a memory in response thereto. Waveforms are then displayed which correspond to these frequency and amplitude values. Various input and display circuits facilitate the display and interpretation of these waveforms.

Abstract: A heterodyne phase lock system is disclosed having a plurality of oscillator circuits, a similar plurality of heterodyne (mixer-filter) circuits representing an input circuit, and a similar plurality of heterodyne circuits representing a control circuit, at least one of the oscillator circuits being a voltage controlled oscillator (VCO) circuit. The heterodyne circuits of the input circuit are cascaded, i.e., linked each to the other, successively, and the heterodyne circuits of the control circuit are likewise cascaded. Each oscillator is linked to a pair of heterodyne circuits, i.e., to one heterodyne circuit in the input circuit and to one heterodyne circuit in the control circuit, and applies a common output signal to said pair of heterodyne circuits.