Abstract: Various aspects of the present disclosure relate to a memory sub-system for block stripe selection and testing. A processing device determines to perform a test for a subset of block stripes of a plurality of block stripes of the memory device, where each block stripe of the plurality of block stripes spans the plurality of dies of the memory device, and the subset of block stripes includes less than all block stripes of the plurality of block stripes. The processing device obtains a first parameter that indicates a first block stripe to be tested and a second parameter that indicates a quantity of block stripes to be tested. The processing device initiates and performs the test for the subset of block stripes using the first parameter and the second parameter.

Abstract: A content addressable memory (CAM) device (400) can sequentially apply command and key data to different sections (404-1 to 404-4). Within each section, CAM cores (402-11 to 402-44) can be sequentially activated. Current surges when transitioning from an idle state to an active state, or vice versa, can be significantly reduced with additional latency but no loss in throughput.