Abstract: A system comprises a plurality of handheld devices including a plurality of transceivers. A control unit may be coupled to a handheld device of the plurality of handheld devices. The system may further include a plurality of end-of-train air devices coupled to a plurality of air brakes. An air manifold may be coupled to the plurality of air brakes. The system may include a controller coupled to the control unit and to the air manifold. A processor may be coupled to the controller and the control unit, and a non-transitory computer readable medium may be coupled to the processor. The non-transitory computer readable medium may include instructions executable to receive information from the control unit corresponding to an air brake test performed on the plurality of end-of-train air devices, determine a status of the air brake test, and generate an inspection form based on the received information and the determined status.

Abstract: A system comprises a plurality of handheld devices including a plurality of transceivers. A control unit may be coupled to a handheld device of the plurality of handheld devices. The system may further include a plurality of end-of-train air devices coupled to a plurality of air brakes. An air manifold may be coupled to the plurality of air brakes. The system may include a controller coupled to the control unit and to the air manifold. A processor may be coupled to the controller and the control unit, and a non-transitory computer readable medium may be coupled to the processor. The non-transitory computer readable medium may include instructions executable to receive information from the control unit corresponding to an air brake test performed on the plurality of end-of-train air devices, determine a status of the air brake test, and generate an inspection form based on the received information and the determined status.

Abstract: A system comprises a plurality of handheld devices including a plurality of transceivers. A control unit may be coupled to a handheld device of the plurality of handheld devices. The system may further include a plurality of end-of-train air devices coupled to a plurality of air brakes. An air manifold may be coupled to the plurality of air brakes. The system may include a controller coupled to the control unit and to the air manifold. A processor may be coupled to the controller and the control unit, and a non-transitory computer readable medium may be coupled to the processor. The non-transitory computer readable medium may include instructions executable to receive information from the control unit corresponding to an air brake test performed on the plurality of end-of-train air devices, determine a status of the air brake test, generate an inspection form based on the received information and the determined status, and transmit the generated inspection form for printing.

Abstract: A system comprises a plurality of handheld devices including a plurality of transceivers. A control unit may be coupled to a handheld device of the plurality of handheld devices. The system may further include a plurality of end-of-train air devices coupled to a plurality of air brakes. An air manifold may be coupled to the plurality of air brakes. The system may include a controller coupled to the control unit and to the air manifold. A processor may be coupled to the controller and the control unit, and a non-transitory computer readable medium may be coupled to the processor. The non-transitory computer readable medium may include instructions executable to receive information from the control unit corresponding to an air brake test performed on the plurality of end-of-train air devices, determine a status of the air brake test, generate an inspection form based on the received information and the determined status, and transmit the generated inspection form for printing.

Abstract: Methods and apparatus are described for providing test access by synchronous test equipment to an asynchronous circuit. Synchronous-to-asynchronous (S2A) conversion circuitry is operable to receive synchronous input data serially from the synchronous test equipment and convert the synchronous input data to asynchronous input data. Asynchronous logic is operable to transmit the asynchronous input data to a first test register in the asynchronous circuit, and to transmit asynchronous output data received from a second test register in the asynchronous circuit. The asynchronous output data results from application of the asynchronous input data to the asynchronous circuit. Operation of the asynchronous logic is synchronized at least in part with a clock signal associated with the synchronous test equipment.

Abstract: A frame analyzer component and a memory management unit process frames received over cable television lines. The frame analyzer component may receive frames that were transmitted over the cable television lines and that were processed by a digital signal processor. The frame analyzer component checks incoming frames or frame fragments for consistency and errors. Results from the frame analyzer component relative to frame fragments may be stored in a context memory. When a later fragment of the frame arrives, the previous context of the frame can be restored and used to continue processing the frame. The memory management unit stores the frames and frame fragments in separate memory management tables.

Abstract: Methods and apparatus are described for providing test access by synchronous test equipment to an asynchronous circuit. Synchronous-to-asynchronous (S2A) conversion circuitry is operable to receive synchronous input data serially from the synchronous test equipment and convert the synchronous input data to asynchronous input data. Asynchronous logic is operable to transmit the asynchronous input data to a first test register in the asynchronous circuit, and to transmit asynchronous output data received from a second test register in the asynchronous circuit. The asynchronous output data results from application of the asynchronous input data to the asynchronous circuit. Operation of the asynchronous logic is synchronized at least in part with a clock signal associated with the synchronous test equipment.

Abstract: A processor reduces or avoids a degradation of computing performance in a computer system using a RISC-based CISC processor by selectively bypassing a CISC-to-RISC translator or decoder and supplying native RISC codes directly to the RISC core. The processor that executes CISC-type instructions on a RISC core includes a native mode Op supply circuit for supplying RISC Ops directly from an instruction memory to a RISC execution engine.