Abstract: Described herein are systems, methods, and computer-readable medium for magnetic resonance (MR) based thermometry. A method for magnetic resonance based thermometry includes: acquiring, by a variable flip-angle T1 mapping sequence, MR data in an area of interest of a subject that is heated by the application of focused ultrasound (FUS) to the brain of the subject, where the MR data includes T1 values over time, and where the acquisition of the MR data includes applying an accelerated three-dimensional ultra-short spiral acquisition sequence with a nonselective excitation pulse; tracking changes in proton resonance frequency and determining, based at least in part on a mathematical relationship established by T1 mapping thermometry, a temperature change in the area of interest over time, and where the temperature change is caused at least in part by a change in the applied FUS.

Abstract: Methods, computing devices, and magnetic resonance imaging systems that improve image quality in turbo spiral echo (TSE) imaging are disclosed. With this technology, a TSE pulse sequence is generated that includes a series of radio frequency (RF) refocusing pulses to produce a corresponding series of nuclear magnetic resonance (NMR) spin echo signals. A gradient waveform including a plurality of segments is generated. The plurality of segments collectively comprise a spiral ring retraced in-out trajectory. During an interval adjacent to each of the series of RF refocusing pulses, a first gradient pulse is generated according to the gradient waveform. The first gradient pulses encode the NMR spin echo signals. An image is then constructed from digitized samples of the NMR spin echo signals obtained based at least in part on the encoding.

Abstract: Described herein are systems, methods, and computer-readable medium for magnetic resonance (MR) based thermometry. In one aspect, in accordance with one embodiment, a method for magnetic resonance based thermometry includes: acquiring, by a variable flip-angle T1 mapping sequence, MR data in an area of interest of a subject that is heated by the application of focused ultrasound (FUS) to the brain of the subject, where the MR data includes T1 values over time, and where the acquisition of the MR data includes applying an accelerated three-dimensional ultra-short spiral acquisition sequence with a nonselective excitation pulse; and determining, based at least in part on a mathematical relationship established by T1 mapping thermometry, a temperature change in the area of interest over time, and where the temperature change is caused at least in part by a change in the applied FUS.

Abstract: Methods, computing devices, and magnetic resonance imaging systems that improve image quality in turbo spiral echo (TSE) imaging are disclosed. With this technology, a TSE pulse sequence is generated that includes a series of radio frequency (RF) refocusing pulses to produce a corresponding series of nuclear magnetic resonance (NMR) spin echo signals. A gradient waveform including a plurality of segments is generated. The plurality of segments collectively comprise a spiral ring retraced in-out trajectory. During an interval adjacent to each of the series of RF refocusing pulses, a first gradient pulse is generated according to the gradient waveform. The first gradient pulses encode the NMR spin echo signals. An image is then constructed from digitized samples of the NMR spin echo signals obtained based at least in part on the encoding.

Abstract: Disclosed herein are devices, systems, and methods for use in a magnetic resonance imaging (MRI)-guided procedure in which focused energy is applied to an area of interest of a subject. Disclosed herein are coupling baths comprising an aqueous solution comprising a plurality of paramagnetic particles dispersed in water, wherein, when magnetic resonance images are collected from the area of interest of the subject for MRI guidance: the coupling bath is located proximate to the area of interest, and the composition, the average particle size, the shape, the concentration, the presence or absence of the capping layer, the identity of the plurality of ligands when the capping layer is present, the average thickness of the capping layer when the capping layer is present, or a combination thereof is/are selected such that the coupling bath reduces or prevents imaging artifacts in the magnetic resonance images for the MRI guidance.

Abstract: Described herein are systems, methods, and computer-readable medium for magnetic resonance (MR) based thermometry. In one aspect, in accordance with one embodiment, a method for magnetic resonance based thermometry includes: acquiring, by a variable flip-angle T1 mapping sequence, MR data in an area of interest of a subject that is heated by the application of focused ultrasound (FUS) to the brain of the subject, where the MR data includes T1 values over time, and where the acquisition of the MR data includes applying an accelerated three-dimensional ultra-short spiral acquisition sequence with a nonselective excitation pulse; and determining, based at least in part on a mathematical relationship established by T1 mapping thermometry, a temperature change in the area of interest over time, and where the temperature change is caused at least in part by a change in the applied FUS.

Abstract: An analog-to-digital converter stage includes: a comparator and logic circuit having first upper and lower unscaled voltage trip points that are different than upper and lower residue voltage trip points; and a switched capacitor circuit. The comparator and logic circuit is configured prior to an initial residue calculation cycle to compare a magnitude of an unscaled input voltage to the first upper and lower unscaled voltage trip points, to generate an initial output bit, and to generate a voltage scaling and gain control signal. The switched capacitor circuit is configured to sample the unscaled input voltage, to receive a reference voltage, and to receive the voltage scaling and gain control signal for selectively controlling a subset of switches of the switched capacitor circuit to scale the unscaled input voltage sample and reference voltage and generate an initial residue voltage during a single operation of the initial residue calculation cycle.

Abstract: A sampling switch circuit uses correlated level shifting. The sampling switch circuit includes: a sampling switch having a first terminal, a control terminal, and an output terminal, wherein the first terminal is connected to an input voltage node; a boosting circuit connected to first and second supply voltage nodes and coupled to the control terminal of the sampling switch; and a correlated level shifting buffer circuit. The correlated level shifting buffer circuit includes: an amplifier having first and second inputs and an output, wherein the first input is connected to the input voltage node, and the output and second input are coupled to the boosting circuit; and a level shifting capacitor coupled to the second input and output of the amplifier, to the boosting circuit, and to a level shifting voltage node.

Abstract: An analog-to-digital converter stage includes: a comparator and logic circuit having first upper and lower unscaled voltage trip points that are different than upper and lower residue voltage trip points; and a switched capacitor circuit. The comparator and logic circuit is configured prior to an initial residue calculation cycle to compare a magnitude of an unscaled input voltage to the first upper and lower unscaled voltage trip points, to generate an initial output bit, and to generate a voltage scaling and gain control signal. The switched capacitor circuit is configured to sample the unscaled input voltage, to receive a reference voltage, and to receive the voltage scaling and gain control signal for selectively controlling a subset of switches of the switched capacitor circuit to scale the unscaled input voltage sample and reference voltage and generate an initial residue voltage during a single operation of the initial residue calculation cycle.

Abstract: A sampling switch circuit uses correlated level shifting. The sampling switch circuit includes: a sampling switch having a first terminal, a control terminal, and an output terminal, wherein the first terminal is connected to an input voltage node; a boosting circuit connected to first and second supply voltage nodes and coupled to the control terminal of the sampling switch; and a correlated level shifting buffer circuit. The correlated level shifting buffer circuit includes: an amplifier having first and second inputs and an output, wherein the first input is connected to the input voltage node, and the output and second input are coupled to the boosting circuit; and a level shifting capacitor coupled to the second input and output of the amplifier, to the boosting circuit, and to a level shifting voltage node.

Abstract: An algorithmic or cyclic data converter uses an RSD stage having a switched capacitor network for efficiently scaling at least one externally supplied reference voltage. A reference voltage is scaled by using capacitor ratios that also function to provide an output voltage used as a residue output of the RSD A/D converter. The residue is used to generate a bit value corresponding to the magnitude of the residue. Two RSD stages cycle back and forth generating a logic value each half clock cycle until the desired bit resolution is achieved. In one form, the RSD stage scales the externally supplied reference voltage only by factors of less than one. In another form, the RSD stage scales the reference voltage by any scaling factor. A reference voltage scaling circuit separate from the RSD stage is avoided.

Abstract: Methods and apparatus are provided for an analog converter. The apparatus comprises a first redundant signed digit (RSD) stage and a configurable block. The configurable block converts to a sample/hold circuit to sample a single ended analog signal. The sampled signal is then scaled, converted to a differential signal and provided to the first RSD stage. The first RSD stage outputs a bit value corresponding to the magnitude of the digital signal. In a next half clock cycle the first RSD stage calculates a residue that is provided to the configurable block. The configurable block is converted to a second redundant signed digit stage and generates a bit value corresponding to the magnitude of the residue provided by the first RSD stage. The first and second RSD stages cycle back and forth generating logic value each half clock cycle until the desired bit resolution is achieved. The configurable block is then converted back to a sample/hold circuit to start another conversion process.

Abstract: A method and corresponding apparatus (10) for generating a pseudo-random number. The method has steps of generating a first bit stream from a number generator (16, 35), combining a predetermined number with the first bit stream to provide a second bit stream and feeding the second bit stream into a feedback port (32) of the number generator (16, 35).

Abstract: An electronic tag (10) receives a data message (18) that has a wake-up section (20) followed by a session section (22). The interrogation signal which carries the data message encodes the wake-up section (20) differently from the session section (22). A power manager (28) decodes the wake-up section (20) using a very low power decoder (34) that remains energized during a standby state. When the power manager (28) detects a predetermined identification code (26), it controls a switching circuit (32) to energize a controller (30). The controller (30) may then decode, process, and respond to information conveyed during the session section (22). If the power manager (28) does not detect the identification code (26), the controller (30) remains de-energized. The power manager (28) also includes a synchronizer (38) which determines when a preamble (24) is detected, and an ID decoder (40) that determines when the wake-up section (20) conveys the predetermined identification code (26).

Abstract: A logic level translator circuit includes capacitive coupling to facilitate rereferencing and differentiating of input logic signals. An input amplifier having complementary devices is responsive to the differentiated signals to provide control signals to a feedback circuit which holds one of the devices in a conductive state and the other in a non-conductive state to provide an output signal having predetermined logic levels. Threshold voltage generating circuits biases each of the devices.

Abstract: An integrated circuit which contains an on-chip clock that operates the integrated circuit at its true maximum speed is disclosed. The integrated circuit operates asynchronously from a processor bus and contains circuitry for interfacing with the processor bus. A clock generator is constructed using information obtained from identifying a slowest signal path of the integrated circuit. The clock may be stopped and started under processor control to permit communication between the IC and processor bus.