Abstract: A digital phase/frequency detector circuit in a phase locked loop comprises multiple bistable devices which are clocked up and down respectively by input and references digital signals to generate square waves. The duty ratio corresponds to the phase/frequency difference and sweeps repetitively between minimum and maximum values as the phase/frequency difference changes monotonically. The square waves are combined logically and additively in the output. The output is integrated to obtain an every increasing output over many cycles of the phase/frequency difference until the maximum is reached depending on the number of bistable devices which are used. Added circuitry is used to avoid coincidence problems in the clocking input and reference digital signals, to minimize resultant irregularities, and hold the bistable devices at maximum or minimum, as appropriate, until the direction of phase/frequency difference reverses.

Abstract: A digital phase/frequency detector circuit in a phase locked loop comprises a logic gate interconnected with a pair of bistable devices clocked respectively by input and reference digital signals to generate a square wave having a duty ratio corresponding to the phase/frequency difference between the two signals. The duty ratio of the square wave sweeps repetitively between minimum and maximum values as the phase/frequency difference changes monotonically. The square wave is integrated to obtain a repetitive sawtooth. To increase the range, circuitry is provided to provide a constant level signal when the peak of a sawtooth is approached and to reset the bistable devices to provide a multiple of the earlier range.

Abstract: A digital phase/frequency detector circuit in a phase locked loop comprises multiple bistable devices which are clocked up and down respectively by input and references digital signals to generate square waves. The duty ratio corresponds to the phase/frequency difference and sweeps repetitively between minimum and maximum values as the phase/frequency difference changes monotonically. The square waves are combined logically and additively in the output. The output is integrated to obtain an ever increasing output over many cycles of the phase/frequency difference until the maximum is reached depending on the number of bistable devices which are used. Added circuitry is used to avoid coincidence problems in the clocking input and reference digital signals, to minimize resultant irregularities, and hold the bistable devices at maximum or minimum, as appropriate, until the direction of phase/frequency difference reverses.

Abstract: A digital phase/frequency detector circuit in a phase locked loop comprises a logic gate interconnected with a pair of bistable devices clocked respectively by input and reference digital signals to generate a square wave having a duty ratio corresponding to the phase/frequency difference between the two signals. The duty ratio of the square wave sweeps repetitively between minimum and maximum values as the phase/frequency difference changes monotonically. The square wave is integrated to obtain a repetitive sawtooth. To increase the range, circuitry is provided to provide a constant level signal when the peak of a sawtooth is approached and to reset the bistable devices to provide a multiple of the earlier range.

Abstract: A three modulus prescaler for a phase-locked loop frequency synthesizer includes a N.sub.0 modulus prescaler inputting into a divide-by-two circuit. A microprocessor and internal logic control a three modulus prescaler synchronizer to receive signals from the divide-by-two circuit and output control commands to the N.sub.0 modulus prescaler so as to cause the N.sub.0 modulus prescaler to divide solely by a first or second modulus, or alternately between said first and second modulus, between output pulses of the divide-by-two circuit to extend the synthesizer's bandwidth.