Abstract: A technology is provided for detecting spoofed satellite signals. An aircraft may be equipped with a top antenna that is adapted to receive satellite signals and a bottom antenna that is adapted to receive terrestrial signals. A signal may be received on the top antenna and the bottom antenna. Relative signal strength between the top antenna and the bottom antenna may be used to differentiate satellite sourced signals from terrestrial sourced signals.

Abstract: A technology is provided for detecting spoofed satellite signals. An aircraft may be equipped with a top antenna that is adapted to receive satellite signals and a bottom antenna that is adapted to receive terrestrial signals. A signal may be received on the top antenna and the bottom antenna. Relative signal strength between the top antenna and the bottom antenna may be used to differentiate satellite sourced signals from terrestrial sourced signals.

Abstract: An aircraft flying assist device, system, and method are disclosed. The aircraft flying assist device can include a computation module to receive data from a distance sensor to determine a height above ground between an aircraft and an underlying ground surface, and to determine a vertical velocity of the aircraft. The aircraft flying assist device can also include a command module to determine a flight instruction command to guide a pilot of the aircraft using at least one of the height above ground and the vertical velocity. The flight instruction command can be an aural command deliverable to the pilot via an audio output mechanism.

Abstract: A vehicle includes a high assurance processing system including a plurality of data processors coupled in parallel, a bridge coupled to the input/output processor, and an input/output processor coupled to the bridge for coupling to a sensor and an effector. Sensor data passes to the bridge through the input/output processor for processing by the parallel data processors, which generate redundant effector data for comparison by the bridge to detect errors. If data matches are found, data is transmitted to the effector.

Abstract: A high assurance processing system includes a plurality of data processors coupled in parallel, a bridge coupled to the plurality of data processors, and an input/output processor coupled to the bridge for coupling to a sensor and an effector. Sensor data passes to the bridge through the input/output processor for processing by the parallel data processors, which generate redundant effector data for comparison by the bridge to detect errors. If data matches are found, data is transmitted to the effector.

Abstract: A modular array processor architecture (10) comprising a plurality of interconnected parallel processing node (11)s that each comprise a control processor (12), an arithmetic processor (13) having an input port (22) for receiving data from an external source that is to be processed, a node memory (14) that also comprises a portion of a distributed global memory, and a network interface (15) coupled between the control processor (12), the arithmetic processor (13), and the node memory (14). Data and control buses (17, 18) are coupled between the arithmetic processors (13) and network interfaces (14) of each of the processing nodes (11). Respective network interfaces (15) link each of the arithmetic processors (13), node memories (14) and control processors (12) together to provide for communication throughout the architecture (10) and permit each node to communicate with the node memories (14) of all other processing nodes (11).

Abstract: A signal processor comprising a split pipelined parallel processor which processes data signals from external signal sources and provides signal processing functions utilizing a plurality of data formats. The signal processor comprises an external interface unit having a serial control port and a plurality of bidirectional parallel ports. The interface unit transfers control and data signals between the signal processor and external devices. The parallel ports are configurable as individual parallel ports or coupled pairs which form a port having the combined data path of the two coupled ports. An arithmetic element controller comprising a microprogram memory and a control program memory is coupled to the interface unit which loads applications programs into the control program memory and executes the programs. The arithmetic element controller controls the processing of control and data signals in the signal processor.

Abstract: An arithmetic element controller which provides for memory address generation for three independent memories of a signal processor and for direct memory access from external devices by way of an interface to the control and data store memories. The arithmetic element controller comprises a first address generator which includes a general purpose address generator circuit and three separate address generator circuits which generates memory addresses for data store, control store and micro store memories, respectively. A second address generator comprises two address generator circuit which comprise memory address logic that generate memory addresses that permit direct memory addressing of the control store and data store memories by way of the interface. A memory access controller is coupled to the two address generators to control access to the respective data store and control store memories by the respective address generators.

Abstract: A multiplier which processes 32 bit operands to provide two 16 bit by 16 bit fixed point products or one 32 bit floating point product during each clock pulse. Two 16 bit by 16 bit fixed point products or one 32 bit floating point product are initiated on every clock pulse and results of the multiplication process are available after a fixed pipeline delay on a continuous basis. The fixed and floating point pipeline operations may also be interleaved. The 32 bit input operands are selected from three external sources or from the last output product. A modified Booth algorithm is implemented employing dual parallel processing paths which are employed to separately produce the 16 bit by 16 bit fixed point products or are combined to produce the 32 bit floating point product. Exponent computations are performed in parallel in the floating point computational mode.