Abstract: High speed networking systems such as PCI-Express and Serial Rapid I/O are based on the exchange of packets across switched networks of high speed serial links. Information in the headers of these packets indicate the kind of transaction they represent. Queuing all received packets in a single queue will cause interactions between transaction types. Indirection can be used create the effect of multiple independent queues from a shared memory. This provides efficient centralized packet storage, while allowing independent processing of different transactions types.

Abstract: High speed networking systems such as PCI-Express and Serial Rapid I/O are based on the exchange of packets across switched networks of high speed serial links. Information in the headers of these packets indicate the kind of transaction they represent. Queuing all received packets in a single queue will cause interactions between transaction types. Indirection can be used create the effect of multiple independent queues from a shared memory. This provides efficient centralized packet storage, while allowing independent processing of different transactions types.

Abstract: A microcomputer is disclosed which has an architecture designed for the efficient performance of digital signal processing applications. The microcomputer contains a primary arithmetic logic unit for performing data operations, and a pair of auxiliary arithmetic logic units for calculating indirect memory address values. A memory bus within the microcomputer has data lines therein, and two sets of address lines; each of the auxiliary arithmetic logic units is connected to one of the sets of address lines. The auxiliary arithmetic logic units are capable of performing circular addressing calculations, by calculating the next memory address from the prior memory address and an index value, and by comparing the next memory address to the limits of the memory block within the circular addressing scheme.

Abstract: A CMOS push-pull output buffer is disclosed, which utilizes two reference nodes in the pull-down side. A first of the reference nodes is dedicated to switching the output from a high to a low logic state. A switching circuit is provided for driving the pull-down transistor associated with the first reference node responsive to the input node transition, but which turns off this pull-down transistor responsive to the output node approaching its final voltage. The second reference node is dedicated for holding the output node low in the DC state. A drive circuit is provided for driving the pull-down transistor associated with this second reference node, but which does not turn on this pull-down transistor until the output node has approached its final voltage, preferably when the first pull-down transistor is turned off.

Abstract: A microcomputer is disclosed which has an architecture designed for the efficient performance of digital signal processing applications. The microcomputer contains a primary arithmetic logic unit for performing data operations, and a pair of auxiliary arithmetic logic units for calculating indirect memory address values. A memory bus within the microcomputer has data lines therein, and two sets of address lines; each of the auxiliary arithmetic logic units is connected to one of the sets of address lines. The auxiliary arithmetic logic units are capable of performing circular addressing calculations, by calculating the next memory address from the prior memory address and an index value, and by comparing the next memory address to the limits of the memory block within the circular addressing scheme.

Abstract: A microcomputer having a dual-channel serial port is disclosed, where both channels of the serial port have the same addressable location. On the transmit side of the serial port, two data words are sequentially written to a two stage first-in first-out memory from the data bus of the microcomputer, when the serial port is addressed. At such time as a frame of data is to be transmitted, the framing signal causes the contents of the two stages of the first-in first-out memory to be loaded into separate transmit shift registers, for serial transmission from the pair of serial output terminals. On the receive side of the serial port, a pair of shift registers each receive serial data at the serial input terminals; at the end of the data frame, the contents of the shift registers are loaded into intermediate receive registers. The contents of the intermediate receive registers are multiplexed onto the data bus, responsive to a read instruction addressing the serial port.