Abstract: A reconfigurable chip level equalizer having circuitry that restores signal orthogonality and eliminates channel interference for a wireless transmitted signal. In at least some embodiments, the reconfigurable chip level equalizer comprises two or more adaptive equalizers, a plurality of operational blocks that interconnect the two or more adaptive equalizers, and a control mechanism that configures the two or more adaptive equalizers and operational blocks according to different signal delay profiles.

Abstract: A system comprising a plurality of adaptive equalizers adapted to couple to a plurality of receive antennas, each of the antennas capable of receiving a multipath delay profile estimate (MDPE), control logic interconnecting at least some of the adaptive equalizers, and a control mechanism that, according to different MDPEs, configures at least some of the adaptive equalizers and control logic.

Abstract: A reconfigurable chip level equalizer having circuitry that restores signal orthogonality and eliminates channel interference for a wireless transmitted signal. In at least some embodiments, the reconfigurable chip level equalizer comprises two or more adaptive equalizers, a plurality of operational blocks that interconnect the two or more adaptive equalizers, and a control mechanism that configures the two or more adaptive equalizers and operational blocks according to different signal delay profiles.

Abstract: A circuit performs threshold normalization of accumulated transition probabilities for a given state of a state transition trellis in a maximum likelihood detector. Threshold normalization may be accomplished by comparison and setting of a single bit in stored transition probabilities. Threshold value comparison may be accomplished by comparing the bth bit of the stored transition probabilities if the threshold value is 2b. When all transition probabilities exceed the threshold value at a stage of the trellis, the transition probabilities are scaled, such as by subtracting the threshold value. Scaling may be implemented by setting the compared bth bits to zero before storage. In general, since accumulated transition probabilities are monotonically increasing for transition probabilities of paths through the trellis in both forward and reverse directions, the present invention may be employed for both threshold normalization of both the forward (&agr;) and reverse (&bgr;) transition probabilities.

Abstract: An iterative decoder limits the range of extrinsic information used for iterative decoding of an encoded frame of data. The iterative decoder includes two or more separate decoders for decoding a received encoded frame of data. Each decoder employs extrinsic information generated from the soft data generated by another decoder decoding the encoded frame of data. The extrinsic information includes an approximate measure of the probability that a particular transmitted bit received by the iterative decoder is a logic 0 or logic 1. The extrinsic information for the bit originates with one decoder and is used by another decoder as external information about that bit. Implementations of the iterative decoder use saturation values to define the boundaries of the range. The saturation values are selected such that either no or relatively small degradation in BER occurs, and the saturation values also define the width of the binary representation of the extrinsic information.

Abstract: An interleaver generates a valid interleaved data address for each iteration i of the mapping by the interleaver without employing a multiplication operation. The interleaver includes an address generator comprises two counters, bit-reverse and index tables, and an accumulation register array. The interleaver further comprises two adders, two registers storing tentative address values addressi and addressi+1, and select logic including a comparator, two buffers, and a multiplexer (mux). Two counters are employed to allow the interleaver to generate at least one valid address for each iteration, and a tentative address is generated from each output value of the two counters. Each iteration generates an output interleaved address. A tentative address is generated by using a portion of the counter value as an address to select a corresponding entry from each of the bit-reverse and index tables and the accumulation register array.

Abstract: Process switch operations common in multiprogramming environments in commercially available data processors, are carried out faster by providing a decision-making capability for determining whether it is later to be restored at the beginning of the process or at the point of interruption. Both hardware and software implementations are disclosed.

Abstract: Process switch operations common in multiprogramming environments in commercially available data processors, are carried out faster herein by providing a decision-making capability for determining whether only a subset or all of the usually saved data actually is to be saved each time a process switch operation is called for. Both hardware and software implementations are disclosed.