Patents by Inventor Steven P. Proffitt

Steven P. Proffitt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit package configuration incorporating shielded circuit element structure
    Patent number: 7141883
    Abstract: An electromagnetically-shielded high-Q inductor may be fabricated within a multi-layer package substrate (MLS). The inductor is preferably constructed as a loop structure on a layer of the MLS, and a shielding structure is formed around the inductor to substantially enclose the inductor in a Faraday cage-like enclosure. The shielding structure includes a top plate formed above the inductor on another layer of the MLS, and a bottom plate formed on yet another layer of the MLS or on a layer of an integrated circuit die which is below and attached to the MLS, preferably using solder bumps. Shielding structure sidewalls may be formed by a ring of stacked vias or via channels. The inductor is preferably connected to stacked vias which provide a connection to the underlying integrated circuit die by way of additional solder bumps and cut-outs through the bottom plate of the shielding structure.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: November 28, 2006
    Assignee: Silicon Laboratories Inc.
    Inventors: Derrick C. Wei, Ying Shi, Kevin G. Smith, Steven P. Proffitt, Axel Thomsen, David M. Pietruszynski, Ligang Zhang
  • Integrated circuit package configuration incorporating shielded circuit element structure
    Publication number: 20040222506
    Abstract: An electromagnetically-shielded high-Q inductor may be fabricated within a multi-layer package substrate (MLS). The inductor is preferably constructed as a loop structure on a layer of the MLS, and a shielding structure is formed around the inductor to substantially enclose the inductor in a Faraday cage-like enclosure. The shielding structure includes a top plate formed above the inductor on another layer of the MLS, and a bottom plate formed on yet another layer of the MLS or on a layer of an integrated circuit die which is below and attached to the MLS, preferably using solder bumps. Shielding structure sidewalls may be formed by a ring of stacked vias or via channels. The inductor is preferably connected to stacked vias which provide a connection to the underlying integrated circuit die by way of additional solder bumps and cut-outs through the bottom plate of the shielding structure.
    Type: Application
    Filed: June 18, 2003
    Publication date: November 11, 2004
    Applicant: Silicon Laboratories, Inc.
    Inventors: Derrick C. Wei, Ying Shi, Kevin G. Smith, Steven P. Proffitt, Axel Thomsen, David M. Pietruszynski