Patents by Inventor Steven Pan

Steven Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12506098
    Abstract: Disclosed are a method for chip packaging having a high-density connection layer and a chip packaging structure, the method comprising S1: preparing a high-density connection layer having multilayered metal wiring layer; S2: preparing a substrate intermediate, and attaching thereto the high-density connection layer; S3: embedding the high-density connection layer into the substrate and preparing a first type pads connected with the multilayered metal wiring layer and a second type pads connected with a wiring layer of the substrate intermediate; S4: inversely mounting the chip on the substrate surface, the first type chip bumps being connected to the first type pads, and the second type chip bumps being connected to the second type pads. Part of the wiring layer inside the substrate is replaced with single-sided or double-sided high-density connection layer to reduce the number of layers and thickness of the substrate, facilitating layout and wiring and improving integration and performance.
    Type: Grant
    Filed: September 20, 2023
    Date of Patent: December 23, 2025
    Assignee: Jiangsu Silicon Integrity Semiconductor Technology Co., Ltd.
    Inventors: Steven Pan, Alex Xie, Peter Chen, Baker Ma, Melvin Mei
  • Publication number: 20250259955
    Abstract: Disclosed are a method for chip packaging having a high-density connection layer and a chip packaging structure, the method comprising S1: preparing a high-density connection layer having multilayered metal wiring layer; S2: preparing a substrate intermediate, and attaching thereto the high-density connection layer; S3: embedding the high-density connection layer into the substrate and preparing a first type pads connected with the multilayered metal wiring layer and a second type pads connected with a wiring layer of the substrate intermediate; S4: inversely mounting the chip on the substrate surface, the first type chip bumps being connected to the first type pads, and the second type chip bumps being connected to the second type pads. Part of the wiring layer inside the substrate is replaced with single-sided or double-sided high-density connection layer to reduce the number of layers and thickness of the substrate, facilitating layout and wiring and improving integration and performance.
    Type: Application
    Filed: September 20, 2023
    Publication date: August 14, 2025
    Inventors: Steven PAN, Alex XIE, Peter CHEN, Baker MA, Melvin MEI
  • Patent number: 7822877
    Abstract: A network processor IC for processing network traffic includes a bus interface and a software programmable search engine communications module. The bus interface of the network processor IC is not specific to a particular search engine and the software programmable search engine communications module enables communications to be conducted between the network processor IC and the search engine via the bus interface according to whatever communications protocol the search engine requires. Using the software programmable search engine communications module, a network processor IC is software programmed to communicate with a particular search engine in a manner that is completely compatible with the search engine.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: October 26, 2010
    Assignee: Bay Microsystems, Inc.
    Inventors: Simon Chong, Steven Pan
  • Publication number: 20080130891
    Abstract: An interface for an integrated circuit (IC) device. The interface includes a scrambler to combine a plurality of plaintext data streams and a pseudorandom key sequence. The scrambler includes a pseudorandom number (PRN) source and a combiner. The PRN source provides a pseudorandom number. The pseudorandom key sequence is based on the pseudorandom number. The combiner receives the plurality of plaintext data streams in parallel and output a corresponding plurality of ciphertext data streams in parallel to another IC device interface. The interface also may include a descrambler to separate a pseudorandom key sequence out of a plurality of parallel ciphertext data streams. By scrambling plaintext data streams and descrambling ciphertext data streams in parallel, the data transmission rate on the IC device may be slower than a data transmission rate used to transfer data between IC devices.
    Type: Application
    Filed: November 5, 2007
    Publication date: June 5, 2008
    Inventors: Alvin Sun, Steven Pan, Frank Lin
  • Publication number: 20080126321
    Abstract: A network processor IC for processing network traffic includes a bus interface and a software programmable search engine communications module. The bus interface of the network processor IC is not specific to a particular search engine and the software programmable search engine communications module enables communications to be conducted between the network processor IC and the search engine via the bus interface according to whatever communications protocol the search engine requires. Using the software programmable search engine communications module, a network processor IC is software programmed to communicate with a particular search engine in a manner that is completely compatible with the search engine.
    Type: Application
    Filed: November 27, 2007
    Publication date: May 29, 2008
    Inventors: Simon Chong, Steven Pan
  • Patent number: D734619
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: July 21, 2015
    Inventor: Steven Pan
  • Patent number: D752351
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: March 29, 2016
    Inventor: Steven Pan