Abstract: A fail-safe counter evaluator is provided to insure proper counting operations by fail-safe counters. The failsafe counter evaluator comprises a first microprocessor, a first counter, a second counter, a second microprocessor and a test channel. The first counter is configured as a counter in operation and disposed in the first microprocessor to receive externally generated count pulses. The second counter is disposed in the first microprocessor and configured to undergo a test. The test channel is configured to send an input test signal to the second counter based on test pulses from the second microprocessor. The first microprocessor and the second microprocessor are synchronized so that to coordinate a start and an end of the test. The second counter is evaluated after the test pulses have been sent to determine if the second counter is operating properly.

Abstract: A fail-safe counter evaluator is provided to insure proper counting operations by fail-safe counters. The failsafe counter evaluator comprises a first microprocessor, a first counter, a second counter, a second microprocessor and a test channel. The first counter is configured as a counter in operation and disposed in the first microprocessor to receive externally generated count pulses. The second counter is disposed in the first microprocessor and configured to undergo a test. The test channel is configured to send an input test signal to the second counter based on test pulses from the second microprocessor. The first microprocessor and the second microprocessor are synchronized so that to coordinate a start and an end of the test. The second counter is evaluated after the test pulses have been sent to determine if the second counter is operating properly.