Patents by Inventor Steven Patrick MAXWELL
Steven Patrick MAXWELL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10910561Abstract: Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments.Type: GrantFiled: May 5, 2017Date of Patent: February 2, 2021Assignee: CROSSBAR, INC.Inventors: Steven Patrick Maxwell, Sung Hyun Jo
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Patent number: 10115819Abstract: A recessed high voltage metal oxide semiconductor (MOS) transistor is provided for use in a two-terminal memory cell. The two-terminal memory cell can include a resistive switching device connected to the recessed MOS transistor. The recessed MOS transistor provides for an increased channel length relative to the transistor size in comparison to a traditional MOS transistor. This allows for a decreased memory cell size while maintaining comparable electrical parameters (threshold voltage, channel length, and leakage) than would otherwise be possible. The recessed MOS transistor can be made as either a NMOS or PMOS device using n-type or p-type materials respectively, where the channel, or inversion layer, is formed by electrons (NMOS) or holes (PMOS) between the source and drain in the transistor.Type: GrantFiled: May 29, 2015Date of Patent: October 30, 2018Assignee: CROSSBAR, INC.Inventors: Harry Yue Gee, Tanmay Kumar, Natividad Vasquez, Jr., Steven Patrick Maxwell, Sundar Narayanan
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Patent number: 9685608Abstract: Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments.Type: GrantFiled: March 12, 2014Date of Patent: June 20, 2017Assignee: CROSSBAR, INC.Inventors: Steven Patrick Maxwell, Sung Hyun Jo
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Patent number: 9601690Abstract: Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichiometric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiOX, where X can be a non-integer greater than zero and less than 2. The sub-oxide can be created in a variety of ways, including various techniques related to growing the sub-oxide, depositing the sub-oxide, or transforming an extant film into the sub-oxide.Type: GrantFiled: October 19, 2015Date of Patent: March 21, 2017Assignee: CROSSBAR, INC.Inventors: Harry Yue Gee, Mark Harold Clark, Steven Patrick Maxwell, Sung Hyun Jo, Natividad Vasquez, Jr.
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Patent number: 9595670Abstract: A method includes patterning a layered structure comprising a monolithic stack including a bottom electrode surrounded by a dielectric material, a switching material, a barrier material, a dielectric hardmask, and a patterned photoresist formed above and adjacent to a portion of the dielectric hardmask. The patterning includes patterning the dielectric hardmask using a first etchant and employing the patterned photoresist as a mask, patterning the barrier material using a second etchant and employing a portion of the dielectric hardmask remaining after the patterning the dielectric hardmask as a mask, and patterning the switching material using ion milling or etching and employing the portion of the dielectric hardmask remaining after the patterning the barrier material as a mask.Type: GrantFiled: July 21, 2014Date of Patent: March 14, 2017Assignee: CROSSBAR, INC.Inventors: Harry Yue Gee, Steven Patrick Maxwell, Natividad Vasquez, Jr., Sundar Narayanan
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Patent number: 9583701Abstract: A memory device comprising a doped conductive polycrystalline layer having an electrically resistive portion, is described herein. By way of example, ion implantation to a subset of the conductive polycrystalline layer can degrade and modify the polycrystalline layer, forming the electrically resistive portion. The electrically resistive portion can include resistive switching properties facilitating digital information storage. Parametric control of the ion implantation can facilitate control over corresponding resistive switching properties of the resistive portion. For example, a projected range or depth of the ion implantation can be controlled, allowing for preferential placement of atoms in the resistive portion, and fine-tuning of a forming voltage of the memory device. As another example, dose and number of atoms implanted, type of atoms or ions that are implanted, the conductive polycrystalline material used, and so forth, can facilitate control over switching characteristics of the memory device.Type: GrantFiled: March 14, 2014Date of Patent: February 28, 2017Assignee: CROSSBAR, INC.Inventors: Harry Yue Gee, Steven Patrick Maxwell, Natividad Vasquez, Jr., Mark Harold Clark
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Publication number: 20160351625Abstract: A recessed high voltage metal oxide semiconductor (MOS) transistor is provided for use in a two-terminal memory cell. The two-terminal memory cell can include a resistive switching device connected to the recessed MOS transistor. The recessed MOS transistor provides for an increased channel length relative to the transistor size in comparison to a traditional MOS transistor. This allows for a decreased memory cell size while maintaining comparable electrical parameters (threshold voltage, channel length, and leakage) than would otherwise be possible. The recessed MOS transistor can be made as either a NMOS or PMOS device using n-type or p-type materials respectively, where the channel, or inversion layer, is formed by electrons (NMOS) or holes (PMOS) between the source and drain in the transistor.Type: ApplicationFiled: May 29, 2015Publication date: December 1, 2016Inventors: Harry Yue Gee, Tanmay Kumar, Natividad Vasquez, JR., Steven Patrick Maxwell, Sundar Narayanan
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Patent number: 9437814Abstract: During fabrication of a two-terminal memory device, a terminal (e.g., bottom terminal) can be formed. After formation of the terminal, a chemical mechanical planarization (CMP) process can be applied that, depending on the composition of the terminal, can cause damage that affect operating characteristics of the finished memory device or cell. In some embodiments, such damage can be removed by one or more post-CMP processes. In some embodiments, such damage can be mitigated so as to prevent the damage from occurring at all, by, e.g., forming a sacrificial layer atop the terminal prior to performing the CMP process. Thus, the sacrificial layer can operate to protect the terminal from damage resulting from the CMP process, with the remainder of the sacrificial layer being removed prior to completing the fabrication of the two-terminal memory device.Type: GrantFiled: August 29, 2014Date of Patent: September 6, 2016Assignee: Crossbar, Inc.Inventors: Harry Yue Gee, Majid Milani, Natividad Vasquez, Jr., Steven Patrick Maxwell, Sundar Narayanan
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Patent number: 9425046Abstract: Techniques for processing silicon germanium (SiGe) thin films to reduce surface roughness thereof are provided herein. In an aspect, a method is disclosed that includes depositing a silicon germanium (SiGe) material upon a surface of a substrate at or below about 450 degrees Celsius, the substrate having a plurality of CMOS devices therein and forming, from the deposited SiGe material, a SiGe material film, wherein the SiGe material film has a jagged surface comprising projections and indentations extended along a direction substantially perpendicular to the surface of the substrate. The method further includes performing a chemical mechanical planarization (CMP) process to the jagged surface of the SiGe material, and reducing variations between the projections and the indentions along the direction substantially perpendicular to the surface of the substrate, and transforming the jagged surface of the SiGe material into a relatively smooth surface, compared to the jagged surface.Type: GrantFiled: July 18, 2014Date of Patent: August 23, 2016Assignee: Crossbar, Inc.Inventors: Harry Yue Gee, Steven Patrick Maxwell, Natividad Vasquez, Jr., Sundar Narayanan
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Patent number: 9401475Abstract: A method of depositing a silver layer includes forming a plurality of openings in a dielectric layer to expose a top surface of a structure comprising a resistive memory layer on top of a p-doped silicon-containing layer on top of a conductive structure, depositing a first metal layer comprising a tungsten layer overlying the top surface of the structure, wherein a first metal material of the first metal layer contacts a resistive memory material of the resistive memory layer and exposing the first metal layer in a bath comprising a solution of silver species having an alkaline pH for a predetermined time to form a silver metal layer from the silver species from the solution overlying the resistive memory material, wherein the silver species is reduced by the first metal material, and wherein the first metal material is solubilized while forming the silver metal layer.Type: GrantFiled: November 18, 2014Date of Patent: July 26, 2016Assignee: Crossbar, Inc.Inventors: Steven Patrick Maxwell, Sung-Hyun Jo, Scott Brad Herner
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Patent number: 9312483Abstract: A method of forming a resistive switching device includes forming a wiring structure over a first dielectric and substrate, forming a junction layer over the wiring structure, forming a resistive switching layer over the junction layer, forming an active metal over the resistive switching layer, forming a tungsten layer over the active metal, forming a barrier layer over the tungsten, depositing a mask over the barrier layer, etching the barrier layer to form a hard mask, etching the junction layer, the resistive switching layer, the active metal layer, and the adhesion layer using the hard mask to form a stack of material, while the adhesion layer maintains adhesion between the barrier layer and the active metal and while side walls of the stack of material have reduced contaminants and have reduced gap regions between the barrier layer and the resistive switching layer.Type: GrantFiled: September 24, 2012Date of Patent: April 12, 2016Assignee: CROSSBAR, INC.Inventor: Steven Patrick Maxwell
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Patent number: 9269898Abstract: Providing for low temperature deposition of silicon-based electrical conductor for solid state memory is described herein. In various disclosed embodiments, the silicon-based conductor can form an electrode of a memory cell, an interconnect between conductive components of an electronic device, a conductive via, a wire, and so forth. Moreover, the silicon-based electrical conductor can be formed as part of a monolithic process incorporating complementary metal oxide semiconductor (CMOS) device fabrication. In particular embodiments, the silicon-based electrical conductor can be a p-type silicon germanium compound, that is activated upon deposition at temperatures compatible with CMOS device fabrication.Type: GrantFiled: July 25, 2014Date of Patent: February 23, 2016Assignee: Crossbar, Inc.Inventors: Steven Patrick Maxwell, Kuk-Hwan Kim, Sung Hyun Jo
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Patent number: 9166163Abstract: Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichimetric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiOX, where X can be a non-integer greater than zero and less than 2. The sub-oxide can be created in a variety of ways, including various techniques related to growing the sub-oxide, depositing the sub-oxide, or transforming an extant film into the sub-oxide.Type: GrantFiled: September 13, 2013Date of Patent: October 20, 2015Assignee: Crossbar, Inc.Inventors: Harry Yue Gee, Mark Harold Clark, Steven Patrick Maxwell, Sung Hyun Jo, Natividad Vasquez, Jr.
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Publication number: 20150228894Abstract: Providing for low temperature deposition of silicon-based electrical conductor for solid state memory is described herein. In various disclosed embodiments, the silicon-based conductor can form an electrode of a memory cell, an interconnect between conductive components of an electronic device, a conductive via, a wire, and so forth. Moreover, the silicon-based electrical conductor can be formed as part of a monolithic process incorporating complementary metal oxide semiconductor (CMOS) device fabrication. In particular embodiments, the silicon-based electrical conductor can be a p-type silicon germanium compound, that is activated upon deposition at temperatures compatible with CMOS device fabrication.Type: ApplicationFiled: July 25, 2014Publication date: August 13, 2015Inventors: Steven Patrick MAXWELL, Kuk-Hwan KIM, Sung Hyun JO
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Patent number: 8889521Abstract: A method of depositing a silver layer includes forming a plurality of openings in a dielectric layer to expose a top surface of a structure comprising a resistive memory layer on top of a p-doped silicon-containing layer on top of a conductive structure, depositing a first metal layer comprising a tungsten layer overlying the top surface of the structure, wherein a first metal material of the first metal layer contacts a resistive memory material of the resistive memory layer and exposing the first metal layer in a bath comprising a solution of silver species having an alkaline pH for a predetermined time to form a silver metal layer from the silver species from the solution overlying the resistive memory material, wherein the silver species is reduced by the first metal material, and wherein the first metal material is solubilized while forming the silver metal layer.Type: GrantFiled: September 14, 2012Date of Patent: November 18, 2014Assignee: Crossbar, Inc.Inventors: Steven Patrick Maxwell, Sung-Hyun Jo
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Patent number: 8883603Abstract: A method for forming a silver structure for a non-volatile memory device includes providing a silver layer material upon a underlying substrate, forming a diffusion barrier material overlying the silver layer material, forming a dielectric hard mask material overlying the diffusion barrier material, subjecting the dielectric hard mask material to a patterning and etching process to form a hard mask and to expose a portion of the diffusion barrier material, subjecting the portion of the diffusion barrier material to an etching process using one or more chlorine bearing species as an etchant material, wherein one or more chloride contaminant species is formed overlying at least a portion of the silver layer material, and reacting the one or more chloride contaminant species with a solution comprising an ammonia species to form a water soluble species, wherein the ammonia species is free from an oxidizing species.Type: GrantFiled: August 1, 2012Date of Patent: November 11, 2014Assignee: Crossbar, Inc.Inventor: Steven Patrick Maxwell
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Publication number: 20140192589Abstract: Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments.Type: ApplicationFiled: March 12, 2014Publication date: July 10, 2014Applicant: Crossbar, Inc.Inventors: Steven Patrick MAXWELL, Sung-Hyun JO
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Patent number: 8765566Abstract: A non-volatile memory device includes first wiring structures elongated in a first direction and separated by a first gap region in a second direction, the first gap region comprising first dielectric material formed in a first process, second wiring structures elongated in a second direction and separated by a second gap region in a first direction, the second gap region comprising second dielectric material formed in a second process, and a resistive switching devices comprising active conductive material, resistive switching material, and a junction material, wherein resistive switching devices are formed at intersections of the first wiring structures and the second wiring structures, wherein the junction material comprising p+ polysilicon material overlying the first wiring material, wherein some resistive switching devices are separated by the first gap region and some resistive switching devices separated by the second gap region.Type: GrantFiled: May 10, 2012Date of Patent: July 1, 2014Assignee: Crossbar, Inc.Inventor: Steven Patrick Maxwell
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Publication number: 20140145135Abstract: Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichimetric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiOX, where X can be a non-integer greater than zero and less than 2. The sub-oxide can be created in a variety of ways, including various techniques related to growing the sub-oxide, depositing the sub-oxide, or transforming an extant film into the sub-oxide.Type: ApplicationFiled: September 13, 2013Publication date: May 29, 2014Applicant: Crossbar, Inc.Inventors: Harry Yue GEE, Mark Harold CLARK, Steven Patrick MAXWELL, Sung Hyun JO, Natividad VASQUEZ, JR.
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Publication number: 20140084233Abstract: A method of forming a resistive switching device includes forming a wiring structure over a first dielectric and substrate, forming a junction layer over the wiring structure, forming a resistive switching layer over the junction layer, forming an active metal over the resistive switching layer, forming a tungsten layer over the active metal, forming a barrier layer over the tungsten, depositing a mask over the barrier layer, etching the barrier layer to form a hard mask, etching the junction layer, the resistive switching layer, the active metal layer, and the adhesion layer using the hard mask to form a stack of material, while the adhesion layer maintains adhesion between the barrier layer and the active metal and while side walls of the stack of material have reduced contaminants and have reduced gap regions between the barrier layer and the resistive switching layer.Type: ApplicationFiled: September 24, 2012Publication date: March 27, 2014Applicant: Crossbar, Inc.Inventor: Steven Patrick MAXWELL