Abstract: A method of creating a vertical semiconductor device, the method includes the steps of performing a LOCal Oxidation of Silicon, LOCOS, process in a vertical trench of a semiconductor material so that oxide material is formed inside the vertical trench, and ledges are formed by the oxide material, inside the vertical trench, as a result of the LOCOS process, so that a lower region of reduced lateral distance is formed between the oxide material, at a base of the trench, depositing the trench with polysilicon and etching the polysilicon downward up to the oxide material using interferometric end point detection, so that polysilicon remains in the lower region.

Abstract: A trench-gate semiconductor device and a manufacturing method therefore is provided. The device includes one or more unit cells, each unit cell includes a trench a first oxide layer arranged on an upper portion of a side wall of the trench, the first oxide layer forming a gate oxide of the unit cell, and a second oxide layer arranged on a lower portion of the side wall and on a bottom of the trench.

Abstract: A Metal Oxide Semiconductor (MOS), Field Effect Transistor (FET), (MOSFET) is provided, including a semiconductor body having a first major surface, and two trenches extending in the semiconductor body from the first major surface, a source region of a first conductivity type adjacent sidewalls of the two trenches at the first major surface, a drain region of the first conductivity type adjacent the two trenches at a position distant from the source region, a channel-accommodating region, of a second conductivity type opposite to the first conductivity type, adjacent the sidewalls of the two trenches between the source region and the drain region, and a first of the two trenches extends further into the semiconductor body compared to a second of the two trenches.

Abstract: The present disclosure relates to a trench metal-oxide-semiconductor field-effect transistor, trench MOSFET, and to a method for manufacturing such transistors. In particular, the present disclosure relates to trench MOSFETs having deep trenches adjacent to the more shallow gate defining trench for obtaining a RESURF effect. According to the present disclosure, an ion implantation region of a charge type similar to that of the drift region is formed in the drift region. The ion implantation region extends below the deep trenches of the trench MOSFET and is vertically aligned with a base of the deep trenches.

Abstract: A trench-gate semiconductor device and a manufacturing method thereof is provided. The device is provided with each unit cell including a first trench, and a second trench extending from a bottom of the first trench. The device includes a gate oxide layer arranged on a first side wall of the first trench, a second oxide layer arranged on a second side wall and bottom of the second trench, a first polysilicon region arranged inside the first trench, separated from the first side wall by the gate oxide layer, forming a gate of the unit cell. The device includes a second polysilicon region arranged inside the second trench, separated from the second side wall and bottom of the second trench by the second oxide layer, forming a buried source of the unit cell, and a third oxide layer arranged in between the first polysilicon region and the second polysilicon region.

Abstract: This disclosure relates to a combined MOS controlled diode (MCD) and MOS transistor semiconductor device and associated method of manufacture. The semiconductor device includes an epitaxial semiconductor layer arranged on a semiconductor substrate and a matrix of trenches formed in the epitaxial layer, with the matrix of trenches including a first plurality of spaced apart parallel trenches and a second plurality of spaced apart parallel trenches. Each of the first plurality of parallel trenches is orthogonal to each of the second plurality of parallel trenches and gate electrodes are arranged in each of the first plurality of spaced apart parallel trenches. Source electrodes are arranged in each of the second plurality of spaced apart parallel trenches.

Abstract: This disclosure relates to a power semiconductor device and a method of manufacturing the same, including: a semiconductor layer defining a first major surface and a drift region and a trench extending from the first major surface into the semiconductor layer. The trench includes a gate electrode surrounded by a gate dielectric configured and arranged to electrically isolate the gate electrode from the semiconductor layer; and a source region extending from the first major surface and abutting a top side-wall portion of the trench, and the source region extends to a depth corresponding to a top surface of the gate electrode.

Abstract: This disclosure relates to a combined MOS controlled diode (MCD) and MOS transistor semiconductor device and associated method of manufacture. The semiconductor device includes an epitaxial semiconductor layer arranged on a semiconductor substrate and a matrix of trenches formed in the epitaxial layer, with the matrix of trenches including a first plurality of spaced apart parallel trenches and a second plurality of spaced apart parallel trenches. Each of the first plurality of parallel trenches is orthogonal to each of the second plurality of parallel trenches and gate electrodes are arranged in each of the first plurality of spaced apart parallel trenches. Source electrodes are arranged in each of the second plurality of spaced apart parallel trenches.

Abstract: This disclosure relates to a power semiconductor device and a method of manufacturing the same, including: a semiconductor layer defining a first major surface and a drift region and a trench extending from the first major surface into the semiconductor layer. The trench includes a gate electrode surrounded by a gate dielectric configured and arranged to electrically isolate the gate electrode from the semiconductor layer; and a source region extending from the first major surface and abutting a top side-wall portion of the trench, and the source region extends to a depth corresponding to a top surface of the gate electrode.

Abstract: A method of manufacturing a semiconductor device comprising source and drain regions (13, 14, 14a) of a first conductivity type, and a channelaccommodating region (15) of a second, opposite conductivity type which separates the source and drain regions. The device comprises a gate (11, 42) which extends adjacent to the channel-accommodating region. The method includes the steps of etching a trench (27) into the semiconductor body of the device at a location laterally spaced from that of the gate (11, 42); and implanting a second conductivity type dopant into the body through the bottom (27b) of the trench to form a second conductivity type localised region (37) in the drain region. The dimensions and doping level of the localised level of the localised region (37) in the finished device is such that the localised region and adjacent portions of the drain region provide a voltage-sustaining spacecharge zone when depleted.

Abstract: Consistent with an example embodiment, a trench FET has source regions arranged above insulated gates in trenches. A body region of opposite conductivity type is arranged between the trenches and a body region is arranged above the body region. Source contact metallisation contacts the source and body contact region. In this way a small cell pitch can be achieved.

Abstract: A method of manufacturing an insulated gate field effect transistor includes providing a substrate (2) having a low-doped region (4), forming insulated gate trenches (8) and implanting dopants of a first conductivity type at the base of the trenches (8). A body implant is implanted in the low-doped regions between the trenches; and diffused to form an insulated gate transistor structure in which the body implant diffuses to form a p-n junction between a body region (22) doped to have the second conductivity type above a drain region (20) doped to have the first conductivity type, the p-n junction being deeper below the first major surface between the trenches than at the trenches. The difference in doping concentration between the low-doped region (4) and the implanted region at the base of the trenches causes the difference in depth of the body-drain p-n junction formed in the diffusion step.

Abstract: An insulated gate field effect transistor has a drain region (2,4), a body region (6) of opposite conductivity type and a source region (8) and an insulated gate (14) extending laterally over the body region (6), defining a channel region (30) extending in the body region (6) from a source end adjacent to the source region (8) to a drain end adjacent to a drain end part (26) of the drain region (4). A conductive shield plate (22) is provided adjacent to the drain end for shielding the gate. Embodiments include a shield plate extension (32) extending over the drain region from the shield plate (22) towards the gate (14).

Abstract: A method of determining liquid absorption of an aggregate comprises providing a shaker apparatus, a vacuum source and a container; placing a sample of the aggregate in the container; adding liquid to the container sufficient to reach a calibration mark on the container; weighing the sample and liquid; mounting the container to the shaker apparatus; connecting the vacuum source to the container; agitating the sample and liquid with the shaker apparatus; applying a vacuum to the sample and liquid with the vacuum source; after the agitation and vacuum steps, adding liquid to the container sufficient to again reach the calibration mark on the container; again weighing the sample and liquid; and subtracting the initial weight of the sample and liquid from the final weight of the sample and liquid in order to determine the liquid absorption of the aggregate.

Abstract: A vertical insulated gate field effect power transistor (3) has a plurality of parallel transistor cells (TC3) with a peripheral gate structure (G31, G2) at the boundary between each two transistor cells (TC3). The gate structure (G31, G32) comprises first (G31) and second (G32) gates isolated from each other so as to be independently operable. The first gate (G31) is a trench-gate (21, 22), and the second gate (G32) has at least an insulated planar gate portion (13, 14). Simultaneous operation of the first (G31) and second (G32) gates forms a conduction channel (23c, 23b) between source (16) and drain (12) regions of the device (3). The device (3) has on-state resistance approaching that of a trench-gate device, better switching performance than a DMOS device, and a better safe operating area than a trench-gate device. The device (3) may be a high side power transistor is series with a low side power transistor (6) in a circuit arrangement (50) (FIG. 14) for supplying a regulated output voltage.

Abstract: A trench-gate semiconductor device, for example a MOSFET or IGBT, having a field plate (24) provided below the trenched gate (8) is manufactured using a process with improved reproducibility. The process includes the steps of etching a first grove (28a) into the semiconductor body (20) for receiving the gate (8), and etching a second groove (28b) into the top major surface (20a) of the semiconductor body (20), the second groove (28b) extending from the bottom of the first groove (28a) and being narrower than the first grove. The invention enables better control of the vertical extent of the gate below the top major surface (20a) of the semiconductor body.

Abstract: A trench-gate vertical power transistor in which the trench-gates (11) are parallel stripes which extend across the active area (100). Source regions (13) and ruggedness regions (15) extend to a source contact surface as alternating stripe areas having a width perpendicular to and fully between each two adjacent parallel stripe trench-gates (11). The ruggedness regions (15) are more heavily doped than the source regions and this enables an increased length of the source regions with a consequent reduction in specific resistance of the transistor. For example, the mesa width (13,15) and the trench-gate (11) width may both be about 0.4 ?m, the ruggedness region (15) length may be about 1 ?m and the source region (13) length may be about 20 ?m. The doping concentration of the p type ruggedness regions (15) may be approximately 10 times greater than the doping concentration of the n type regions (13), for example about 1021 cm?3 and about 1020 cm?3 respectively.

Abstract: A trench-gate semiconductor device, for example a MOSFET or IGBT, includes a semiconductor body (20) having a drain region (4) comprising a drain drift region (4a) and a drain contact region (4b). An insulated field plate (24) is included in the trench (10) between the gate (8) and the drain contact region (4b), wherein the field plate (24) is for connection to a bias potential greater than the gate potential and near to the bulk breakdown voltage of the drain drift region (4a). The field plate (24) causes the potential drop across the drain drift region (4a) to be spread considerably more evenly, particularly at applied voltages greater than the bulk breakdown voltage, thereby substantially increasing the breakdown voltage of the device.

Abstract: A cellular MOSFET device has a cellular area (CA) comprising active MOSFET cells, and one or more Schottky diode areas (SA) accommodated within a deep end region (15) at a lateral boundary of this cellular area (CA). This deep end region (150) is laterally divided so as to accommodate the diode area (SA) therein. A diode portion (14d) of the first conductivity type of the drain region (14) extends upwardly through the laterally-divided deep end region (150) that is of the second conductivity type. The Schotty barrier (100) formed with this diode portion (14d) terminates laterally in the laterally-divided portions (150f) of the deep end region (150) which serve as a guard region and field-relief region for the Schottky diode.