Patents by Inventor Steven Poon

Steven Poon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070183106
    Abstract: A multi-stack power supply clamp circuit for providing electrostatic discharge (ESD) protection to enhance performance of advanced submicron processes is provided. The clamp circuit includes a bias voltage generator with low leakage and high current drive capabilities, and means to lighten current load on the voltage generator through reduced gate leakage. The bias voltage generator includes a differential amplifier. The multi-stack clamp circuit provides voltage-tolerant ESD protection with optimized leakage, reduced sensitivity to operating conditions, and tolerance of increased gate current in new process technologies.
    Type: Application
    Filed: April 12, 2007
    Publication date: August 9, 2007
    Applicant: INTEL CORPORATION
    Inventors: Steven Poon, Timothy Maloney
  • Publication number: 20060220762
    Abstract: Apparatus and systems, as well as methods and articles, may operate to transmit an initial pulse to a directional coupler, where the initial pulse has an initial amplitude and a timed overshoot of a selected duration. Further activities may include stepping down the initial amplitude to an amplitude approximately equal to the initial amplitude times a mode reflection coefficient squared. A tuning stub may be coupled to a charge line to transmit the initial pulse, and decoupled from the charge line to refrain from receiving an echo pulse associated with the initial pulse.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 5, 2006
    Inventors: Timothy Maloney, Steven Poon
  • Publication number: 20060072258
    Abstract: A multi-stack power supply clamp circuit for providing electrostatic discharge (ESD) protection to enhance performance of advanced submicron processes is provided. The clamp circuit includes a bias voltage generator with low leakage and high current drive capabilities, and means to lighten current load on the voltage generator through reduced gate leakage. The bias voltage generator has includes a differential amplifier. The multi-stack clamp circuit provides voltage-tolerant ESD protection with optimized leakage, reduced sensitivity to operating conditions, and tolerance of increased gate current in new process technologies.
    Type: Application
    Filed: September 30, 2004
    Publication date: April 6, 2006
    Inventors: Steven Poon, Timothy Maloney