Patents by Inventor Steven Przybylski
Steven Przybylski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8984249Abstract: A plurality of memory devices (e.g., DRAMs, SRAMs, NAND Flash, NOR Flash) is serially interconnected. Each of the interconnected devices receives a device identifier (ID) and latches it as its ID. Each device includes a circuit for calculating another ID or an incremented ID to generate it. The generated ID is transferred to another device and the ID is incremented in each of the devices in the serial interconnection. The last device in the interconnection provides a last generated ID that is provided to a memory controller having a recognition circuit that recognizes the total number of the serially interconnected devices, from the provided last generated ID. The recognition circuit recognizes the total output latency of the devices in the serial interconnection.Type: GrantFiled: December 20, 2006Date of Patent: March 17, 2015Assignee: NovaChips Canada Inc.Inventors: Hong Beom Pyeon, HakJune Oh, Jin-Ki Kim, Steven Przybylski
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Patent number: 8902910Abstract: In a ring-of-clusters network topology, groups of slave devices are accessed in parallel, such that the latency around the ring is proportional to the number of clusters and not proportional to the number of integrated circuits. The devices of a cluster share input and output ring segments such that packets arriving on the input segment are received and interpreted by all the devices in a cluster. In other embodiments, none, some or all but one slaves per cluster are asleep or otherwise disabled so that they do not input and interpret incoming packets. Regardless, in all embodiments, the slaves of a cluster cooperate, potentially under the controller's direction, to ensure that at most one of them is actively driving the output segment at any given time. The devices may be addressed through a device ID, a cluster ID, or a combination thereof. Embodiments of the invention are suited to exploit multi-chip module implementations and forms of vertical circuit stacking.Type: GrantFiled: October 18, 2013Date of Patent: December 2, 2014Assignee: Conversant Intellectual Property Management Inc.Inventor: Steven Przybylski
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Publication number: 20140325178Abstract: A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.Type: ApplicationFiled: July 14, 2014Publication date: October 30, 2014Inventors: Steven PRZYBYLSKI, Roland SCHUETZ, HakJune OH, Hong Beom PYEON
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Patent number: 8812768Abstract: A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.Type: GrantFiled: February 19, 2008Date of Patent: August 19, 2014Assignee: Conversant Intellectual Property Management Inc.Inventors: Steven Przybylski, Roland Schuetz, HakJune Oh, Hong Beom Pyeon
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Error detection and correction codes for channels and memories with incomplete error characteristics
Patent number: 8806305Abstract: A channel has a first and a second end. The first end of the channel is coupled to a transmitter. The channel is capable of transmitting symbols selected from a symbol set from the first end to the second end. The channel exhibits incomplete error introduction properties. A code comprises a set of code words. The elements of the set of code words are one or more code symbols long. The code symbols are members of the symbol set. The minimum modified Hamming separation between the elements of the set of code words in light of the error introduction properties of the channel is greater than the minimum Hamming distance between the elements of the set of code words. A memory device, a method of using the channel, and a method of generating the code are also described.Type: GrantFiled: April 18, 2013Date of Patent: August 12, 2014Assignee: Conversant Intellectual Property Management Inc.Inventor: Steven Przybylski -
Publication number: 20140195715Abstract: A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.Type: ApplicationFiled: February 5, 2014Publication date: July 10, 2014Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventors: Jin-Ki KIM, HakJune OH, Hong Beom PYEON, Steven PRZYBYLSKI
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Publication number: 20140115190Abstract: In a ring-of-clusters network topology, groups of slave devices are accessed in parallel, such that the latency around the ring is proportional to the number of clusters and not proportional to the number of integrated circuits. The devices of a cluster share input and output ring segments such that packets arriving on the input segment are received and interpreted by all the devices in a cluster. In other embodiments, none, some or all but one slaves per cluster are asleep or otherwise disabled so that they do not input and interpret incoming packets. Regardless, in all embodiments, the slaves of a cluster cooperate, potentially under the controller's direction, to ensure that at most one of them is actively driving the output segment at any given time. The devices may be addressed through a device ID, a cluster ID, or a combination thereof. Embodiments of the invention are suited to exploit multi-chip module implementations and forms of vertical circuit stacking.Type: ApplicationFiled: October 18, 2013Publication date: April 24, 2014Applicant: MOSAID Technologies IncorporatedInventor: Steven PRZYBYLSKI
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Patent number: 8671252Abstract: A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.Type: GrantFiled: February 26, 2013Date of Patent: March 11, 2014Assignee: Mosaid Technologies IncorporatedInventors: Jin-ki Kim, Hakjune Oh, Hong Beom Pyeon, Steven Przybylski
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Patent number: 8594110Abstract: In a ring-of-clusters network topology, groups of slave devices are accessed in parallel, such that the latency around the ring is proportional to the number of clusters and not proportional to the number of integrated circuits. The devices of a cluster share input and output ring segments such that packets arriving on the input segment are received and interpreted by all the devices in a cluster. In other embodiments, none, some or all but one slaves per cluster are asleep or otherwise disabled so that they do not input and interpret incoming packets. Regardless, in all embodiments, the slaves of a cluster cooperate, potentially under the controller's direction, to ensure that at most one of them is actively driving the output segment at any given time. The devices may be addressed through a device ID, a cluster ID, or a combination thereof. Embodiments of the invention are suited to exploit multi-chip module implementations and forms of vertical circuit stacking.Type: GrantFiled: January 11, 2008Date of Patent: November 26, 2013Assignee: MOSAID Technologies IncorporatedInventor: Steven A. Przybylski
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ERROR DETECTION AND CORRECTION CODES FOR CHANNELS AND MEMORIES WITH INCOMPLETE ERROR CHARACTERISTICS
Publication number: 20130232393Abstract: A channel has a first and a second end. The first end of the channel is coupled to a transmitter. The channel is capable of transmitting symbols selected from a symbol set from the first end to the second end. The channel exhibits incomplete error introduction properties. A code comprises a set of code words. The elements of the set of code words are one or more code symbols long. The code symbols are members of the symbol set. The minimum modified Hamming separation between the elements of the set of code words in light of the error introduction properties of the channel is greater than the minimum Hamming distance between the elements of the set of code words. A memory device, a method of using the channel, and a method of generating the code are also described.Type: ApplicationFiled: April 18, 2013Publication date: September 5, 2013Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventor: Steven PRZYBYLSKI -
Error detection and correction codes for channels and memories with incomplete error characteristics
Patent number: 8429495Abstract: A channel has a first and a second end. The first end of the channel is coupled to a transmitter. The channel is capable of transmitting symbols selected from a symbol set from the first end to the second end. The channel exhibits incomplete error introduction properties. A code comprises a set of code words. The elements of the set of code words are one or more code symbols long. The code symbols are members of the symbol set. The minimum modified Hamming separation between the elements of the set of code words in light of the error introduction properties of the channel is greater than the minimum Hamming distance between the elements of the set of code words. A memory device, a method of using the channel, and a method of generating the code are also described.Type: GrantFiled: October 19, 2010Date of Patent: April 23, 2013Assignee: MOSAID Technologies IncorporatedInventor: Steven Przybylski -
Patent number: 8407395Abstract: A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.Type: GrantFiled: August 22, 2007Date of Patent: March 26, 2013Assignee: Mosaid Technologies IncorporatedInventors: Jin-Ki Kim, HakJune Oh, Hong Beom Pyeon, Steven Przybylski
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ERROR DETECTION AND CORRECTION CODES FOR CHANNELS AND MEMORIES WITH INCOMPLETE ERROR CHARACTERISTICS
Publication number: 20120096330Abstract: A channel has a first and a second end. The first end of the channel is coupled to a transmitter. The channel is capable of transmitting symbols selected from a symbol set from the first end to the second end. The channel exhibits incomplete error introduction properties. A code comprises a set of code words. The elements of the set of code words are one or more code symbols long. The code symbols are members of the symbol set. The minimum modified Hamming separation between the elements of the set of code words in light of the error introduction properties of the channel is greater than the minimum Hamming distance between the elements of the set of code words. A memory device, a method of using the channel, and a method of generating the code are also described.Type: ApplicationFiled: October 19, 2010Publication date: April 19, 2012Inventor: Steven PRZYBYLSKI -
Publication number: 20090180483Abstract: In a ring-of-clusters network topology, groups of slave devices are accessed in parallel, such that the latency around the ring is proportional to the number of clusters and not proportional to the number of integrated circuits. The devices of a cluster share input and output ring segments such that packets arriving on the input segment are received and interpreted by all the devices in a cluster. In other embodiments, none, some or all but one slaves per cluster are asleep or otherwise disabled so that they do not input and interpret incoming packets. Regardless, in all embodiments, the slaves of a cluster cooperate, potentially under the controller's direction, to ensure that at most one of them is actively driving the output segment at any given time. The devices may be addressed through a device ID, a cluster ID, or a combination thereof. Embodiments of the invention are suited to exploit multi-chip module implementations and forms of vertical circuit stacking.Type: ApplicationFiled: January 11, 2008Publication date: July 16, 2009Inventor: Steven A. Przybylski
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Publication number: 20080201548Abstract: A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.Type: ApplicationFiled: February 19, 2008Publication date: August 21, 2008Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventors: Steven PRZYBYLSKI, Roland SCHUETZ, HakJune OH, Hong Beom PYEON
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Publication number: 20080155219Abstract: A plurality of memory devices (e.g., DRAMs, SRAMs, NAND Flash, NOR Flash) is serially interconnected. Each of the interconnected devices receives a device identifier (ID) and latches it as its ID. Each device includes a circuit for calculating another ID or an incremented ID to generate it. The generated ID is transferred to another device and the ID is incremented in each of the devices in the serial interconnection. The last device in the interconnection provides a last generated ID that is provided to a memory controller having a recognition circuit that recognizes the total number of the serially interconnected devices, from the provided last generated ID. The recognition circuit recognizes the total output latency of the devices in the serial interconnection.Type: ApplicationFiled: December 20, 2006Publication date: June 26, 2008Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventors: Hong Beom PYEON, HakJune OH, Jin-Ki KIM, Steven A. PRZYBYLSKI
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Publication number: 20080049505Abstract: A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.Type: ApplicationFiled: August 22, 2007Publication date: February 28, 2008Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventors: Jin-Ki KIM, HakJune OH, Hong Beom PYEON, Steven PRZYBYLSKI
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Patent number: 5113506Abstract: A cache-based computer architecture is disclosed in which the address generating unit and the tag comparator are packaged together and separately from the cache RAMs. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, the address generating unit and the tag comparator logic. Further, interleaved access to more than one cache may be accomplished on the external address, data and the tag busses.Type: GrantFiled: March 9, 1990Date of Patent: May 12, 1992Assignee: MIPS Computer Systems, Inc.Inventors: John P. Moussouris, Lester M. Crudele, Steven A. Przybylski
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Patent number: 4959779Abstract: A CPU or other function unit is disclosed which follows one data ordering scheme internally, and in which incoming and/or outgoing data pass through a data order conversion unit for adapting it to a selectable external data ordering scheme. The means for specifying the external data ordering scheme is accessible from outside the physical package(s) in which the functional unit is housed. The data order conversion unit may comprise a load aligner and/or a store aligner, one or both of which may comprise means for shifting informational units of a smaller size within informational units of a larger size. The shift amount may derive from the low order address bits and may be altered depending on the external data ordering means selected.Type: GrantFiled: November 28, 1988Date of Patent: September 25, 1990Assignee: Mips Computer Systems, Inc.Inventors: Larry B. Weber, Craig C. Hansen, Thomas J. Riordan, Steven A. Przybylski
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Patent number: 4953073Abstract: A cache-based computer architecture has the address generating unit and the tag comparator packaged together and separately from the cache RAMS. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, the address generating unit and the tag comparator logic. Further, interleaved access to more than one cache may be accomplished on the external address, data and tag busses.Type: GrantFiled: February 6, 1986Date of Patent: August 28, 1990Assignee: MIPS Computer Systems, Inc.Inventors: John P. Moussouris, Lester M. Crudele, Steven A. Przybylski