Abstract: In one embodiment, a system includes a controller and logic integrated with and/or executable by the controller. The logic is configured to perform iterative decoding on encoded data to obtain decoded data. At least three decoding operations are performed in the iterative decoding, with the decoding operations being selected from a group consisting of: C1 decoding and C2 decoding. The logic is also configured to perform post-decoding error diagnostics on a first portion of the decoded data in response to not obtaining a valid product codeword in the first portion after the iterative decoding of the encoded data. Other systems, methods, and computer program products for producing post-decoding error signatures are presented in accordance with more embodiments.

Abstract: In one embodiment, a system includes a controller and logic integrated with and/or executable by the controller, the logic being configured to write a data set to a first write section of a magnetic medium, the data set including a plurality of sub data sets, each including a data array organized in rows and columns, each row of the data array including a CWI-4. A first portion of the data set is stored as CWI-4 sets to the first write section of the magnetic medium with first headers. The logic is also configured to rewrite at least some of the data set as rewritten CWI-4 sets to a rewrite section of the magnetic medium as rewritten CWI-4s having corresponding rewrite headers. A length of any one of the rewrite headers is greater than a length of any one of the first headers.

Abstract: A plurality of fuses are arranged in pairs and configured such that each pair of fuses represents a data bit when one fuse of the pair is blown; represents an un-programmed bit when no fuse of the pair is blown; and represents a zero-ized bit when both fuses of the pair are blown. A fuse programming system programs the fuses of the pairs such that each pair represents a bit, comprising blowing a first fuse of a pair to represent a “1” bit, blowing a second fuse of a pair to represent a “0” bit, and blowing both fuses of a pair to represent a zero-ized pair, whereby if neither fuse of a pair is blown represents a null, un-programmed bit.

Abstract: Writing data to magnetic tape is performed by receiving data from a host, establishing sub data sets, computing C1 and C2 ECC, forming Codeword Quad sets, writing a beginning Data Set Separator to a magnetic tape, writing a plurality of contiguous instances of the CQ Set to the magnetic tape and writing a closing DSS. The number of instances of each Codeword Pair is increased, thereby allowing the benefits of writing short tape records and improving reading reliability while reducing susceptibility to mis-tracking errors and large defects, and while reducing the negative impact on data reliability. Otherwise unused latency times are utilizing and therefore no performance penalty is incurred.

Abstract: A magnetic tape drive having a tape drive system for moving magnetic tape, tape read/write and servo system, tape cartridge load/unload systems, I/O communications, memory; and a control system, operates in three modes to conserve energy consumption. A first low power mode powers the I/O communications, the memory, and the control system. If a magnetic tape cartridge is in loaded position in the magnetic tape drive, the second low power mode powers the same as the first low power mode, and additionally powers the tape drive system to apply tension to a magnetic tape of the magnetic tape cartridge. In the first and the second low power modes, the control system operates the I/O communications, the memory and the control system to respond to and execute commands received at the I/O communications if the commands are executable without magnetic tape access. The third, full power mode, is entered if a command received at the I/O communications requires magnetic tape access.

Abstract: Writing data to magnetic tape is performed by receiving data from a host, establishing sub data sets, computing C1 and C2 ECC, forming Codeword Quad sets, writing a beginning Data Set Separator to a magnetic tape, writing a plurality of contiguous instances of the CQ Set to the magnetic tape and writing a closing DSS. The number of instances of each Codeword Pair is increased, thereby allowing the benefits of writing short tape records and improving reading reliability while reducing susceptibility to mis-tracking errors and large defects, and while reducing the negative impact on data reliability. Otherwise unused latency times are utilizing and therefore no performance penalty is incurred.

Abstract: A method and apparatus for accurately locating targeted append points in a tape drive. The effects of interlayer slip (ILS) are eliminated and smaller IBGs are possible thus providing increased data capacity for a given tape cartridge. A coarse tachometer count is used in combination with the read dataflow to accurately locate the proper append point even with a small IBG size. The appended data are assured to be written using the proper tape velocity which virtually eliminates improper write appends and read temporary errors previously caused by ILS effects. The solution also guarantees that customer data previously written to the tape are not accidentally overwritten.

Abstract: A method and apparatus which first calculates track to track skew in a tape device and then uses the results of that calculation to adjust the windows for detection of sync and resync characters. The system makes use of global circuitry which adjusts the sync and resync windows for all tracks based upon the skew calculation. In the case of the windows used for detecting resyncs, when skew is determined to be large, the global resync window must span a larger time period to account for the skew in detecting resync marks. Conversely, when there is little or no skew present, the windows for resync detection can be narrowed. Normally, the track logic utilizes its own local windows to detect resyncs. If a track misses a resync, however, it must use the global resync window to determine the next resync location. Once the tracks are resynchronized, control can return to local track circuitry to maintain synchronization.

Abstract: An apparatus and method for detecting and validating formatted blocks during read/write data operations in a magnetic tape data storage system includes component functionality for reading and writing data on a magnetic tape medium in a plurality of modes, including a read-only (R) mode and a read-while-write (RWW) mode, the data being arranged in one or more tracks in a sequence of formatted blocks. In preferred embodiments, formatted block detection and validation is performed by appropriate logic circuitry configured to detect at least one formatting entity representing an inter-block gap, a block acquisition burst, a synchronization character, or any other desired formatting entity, using first and second programmable detection thresholds that are the same or substantially the same in both the R and RWW modes.

Abstract: A method and system for accurately reading and storing data as multiple data blocks on a removable data storage medium mounted within a data storage system. Each data block includes an initial acquisition data character and multiple diverse synchronization characters/bursts and adjacent data blocks are separated by a unique interblock gap character. A multimodal interblock gap character detection circuit is provided which may operate in a normal mode of operation or a stringent mode of operation, wherein an enhanced degree of certainty is required for detection of the interblock gap character. A predicted time window of occurrence for a next interblock gap character is generated in response to detection of an initial acquisition data character and at least one synchronization character within a data block. Additionally, a global clock count signal based upon multiple track outputs is generated each time a resynchronization burst is encountered.

Abstract: A method and system for detecting and validating multibit acquisition burst sequences which precede and follow each data block in a multitrack data storage system. An acquisition sequence pattern detection circuit is utilized to provide an indication of acquisition burst sequence detection in response to an occurrence of an accurate sequence of a selected number of acquisition burst sequence bits. A latch is utilized to store the pattern criteria indication for each associated track and the latch outputs are then combined in a logic circuit to provide a composite burst pattern error indication signal.

Abstract: A method and apparatus which first calculates track to track skew in a tape device and then uses the results of that calculation to adjust the windows for detection of sync and resync characters. The system makes use of global circuitry which adjusts the sync and resync windows for all tracks based upon the skew calculation. In the case of the windows used for detecting resyncs, when skew is determined to be large, the global resync window must span a larger time period to account for the skew in detecting resync marks. Conversely, when there is little or no skew present, the windows for resync detection can be narrowed. Normally, the track logic utilizes its own local windows to detect resyncs. If a track misses a resync, however, it must use the global resync window to determined the next resync location. Once the tracks are resynchronized, control can return to local track circuitry to maintain synchronization.

Abstract: A zero-crossing detector for asynchronous detection of threshold transitions in a digitally sampled signal waveform. The Asynchronous Digital Threshold Detector (ADTD) receives a digitized self-clocking data readback waveform and provides the relative location of a zero-crossing within the sample period where it occurs. The digital output, which is useful for recovering data and clock signals, is in a digital form that can be used directly by a certain class of asynchronous digital phase detector systems. The ADTD is entirely digital and can be embodied in a low power configuration using CMOS technology.

Abstract: Pointer control logic for error correcting codes includes a set of registers the contents of which are rotated whenever data from a track with a pointer are processed. In that manner, a given one register always contains pointer data for the track under consideration (if that track has a pointer). The pointer control logic includes programmable initializing values to stress write operations as desired. Further, the logic contains multiple and programmable pointer dropping thresholds so that pointer registers can be candidates for dropping dependent on the type of error encountered. Provision is made for extending pointer life when errors are encountered, registers are full, and no register has dropped below the pointer dropping threshold.

Abstract: A buffer memory is used to store data from the input/output device arrayed corresponding to the data rate of said input/output data device. A threshold is selected for beginnig an unload cycle of the buffer memory which will permit said buffer memory contents to be completely transferred at the higher channel data rate to the channel during the remaining time additional data is being accumulated in the memory. The threshold selection is adaptive such that subsequent data block lengths are utilized to calculate a new threshold maintaining data transfer rates from the input/output device into the channel at an optimum value.