Patents by Inventor Steven R. Bristow
Steven R. Bristow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8207725Abstract: A tester includes a device under test (DUT) power supply (DPS) with and input and output includes an amplifier configured to set an output voltage of the DPS output equal to an input voltage for the DPS. The DPS has a first output stage coupled to the amplifier and configured to source and sink current at the output of the DPS between a first voltage rail and a third voltage rail. The DPS has a second output stage coupled to the amplifier and configured to source and sink current to the output of the DPS between a second voltage rail and the third voltage rail. A selection device is configured to enable the first and second output stages based on a selection input signal. The selection device is situated outside of the first and the second output stages.Type: GrantFiled: August 16, 2011Date of Patent: June 26, 2012Assignee: Intersil Americas Inc.Inventors: Patrick Sullivan, Steven R. Bristow, William R. Creek, Jeffrey Allen King
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Publication number: 20110298483Abstract: A tester includes a device under test (DUT) power supply (DPS) with and input and output includes an amplifier configured to set an output voltage of the DPS output equal to an input voltage for the DPS. The DPS has a first output stage coupled to the amplifier and configured to source and sink current at the output of the DPS between a first voltage rail and a third voltage rail. The DPS has a second output stage coupled to the amplifier and configured to source and sink current to the output of the DPS between a second voltage rail and the third voltage rail. A selection device is configured to enable the first and second output stages based on a selection input signal. The selection device is situated outside of the first and the second output stages.Type: ApplicationFiled: August 16, 2011Publication date: December 8, 2011Applicant: INTERSIL AMERICAS INC.Inventors: Patrick Sullivan, Steven R. Bristow, William Robert Creek, Jeffrey Allen King
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Patent number: 7999530Abstract: A power supply with and input and output includes an amplifier configured to set an output voltage of the power supply output equal to a fixed input voltage for the power supply. The power supply has a first output stage coupled to the amplifier and configured to source and sink current at the output of the power supply between a first voltage rail and a third voltage rail. The power supply has a second output stage coupled to the amplifier and configured to source and sink current to the output of the power supply between a second voltage rail and the third voltage rail. A selection device is configured to enable the first and second output stages based on a selection input signal. The selection device is situated outside of the first and the second output stages.Type: GrantFiled: March 20, 2009Date of Patent: August 16, 2011Assignee: Intersil Americas Inc.Inventors: Patrick Sullivan, Steven R. Bristow, William Robert Creek, Jeffrey Allen King
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Publication number: 20100066448Abstract: A power supply with and input and output includes an amplifier configured to set an output voltage of the power supply output equal to a fixed input voltage for the power supply. The power supply has a first output stage coupled to the amplifier and configured to source and sink current at the output of the power supply between a first voltage rail and a third voltage rail. The power supply has a second output stage coupled to the amplifier and configured to source and sink current to the output of the power supply between a second voltage rail and the third voltage rail. A selection device is configured to enable the first and second output stages based on a selection input signal. The selection device is situated outside of the first and the second output stages.Type: ApplicationFiled: March 20, 2009Publication date: March 18, 2010Applicant: INTERSIL AMERICAS INC.Inventors: Patrick G. Sullivan, Steven R. Bristow, William Robert Creek, Jeffrey Allen King
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Patent number: 6754868Abstract: A method and apparatus are provided for high speed testing of devices having either logic circuits, memory arrays or both. Apparatus (100) includes: (i) pin electronics (P/Es 145) each coupling the apparatus to one of a number of pins (115) on device (110); (ii) timing and format circuits (T/Fs 150) for mapping a signal to one of P/Es (100); (iii) pattern generator (140) having a number of outputs for outputting signals for testing device (110); (iv) pin scrambling circuit (155) between pattern generator (140) and T/Fs (150), the pin scrambling circuit capable of mapping at least two signals from any of the pattern generator outputs to any of the T/Fs; and (v) clock (135) for providing a clock signal having a clock cycle to pattern generator (140) and T/Fs (150). T/Fs (150) are capable of switching the signals coupled to P/Es (100) at least twice each clock cycle.Type: GrantFiled: June 29, 2001Date of Patent: June 22, 2004Assignee: Nextest Systems CorporationInventors: Steven R. Bristow, Paul Magliocco, Seth W. Craighead
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Publication number: 20030005381Abstract: A method and apparatus are provided for high speed testing of devices having either logic circuits, memory arrays or both. Apparatus (100) includes: (i) pin electronics (P/Es 145) each coupling the apparatus to one of a number of pins (115) on device (110); (ii) timing and format circuits (T/Fs 150) for mapping a signal to one of P/Es (100); (iii) pattern generator (140) having a number of outputs for outputting signals for testing device (110); (iv) pin scrambling circuit (155) between pattern generator (140) and T/Fs (150), the pin scrambling circuit capable of mapping at least two signals from any of the pattern generator outputs to any of the T/Fs; and (v) clock (135) for providing a clock signal having a clock cycle to pattern generator (140) and T/Fs (150). T/Fs (150) are capable of switching the signals coupled to P/Es (100) at least twice each clock cycle.Type: ApplicationFiled: June 29, 2001Publication date: January 2, 2003Inventors: Steven R. Bristow, Paul Magliocco, Seth W. Craighead
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Patent number: 4809221Abstract: A unique timing system is provided which allows for a user to program timing events with variable periods and edges from a fixed frequency clock, and having resolution greater than that of the fixed reference frequency. Delay elements, which are inherently expensive, inaccurate, and require repeated calibration, are minimized.Type: GrantFiled: April 26, 1988Date of Patent: February 28, 1989Assignee: Megatest CorporationInventors: Paul D. Magliocco, Steven R. Bristow
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Patent number: 4779221Abstract: A unique timing system is provided which allows for a user to program timing events with variable periods and edges from a fixed frequency clock, and having resolution greater than that of the fixed reference frequency. Delay elements, which are inherently expensive, inaccurate, and require repeated calibration, are minimized.Type: GrantFiled: January 28, 1987Date of Patent: October 18, 1988Assignee: Megatest CorporationInventors: Paul D. Magliocco, Steven R. Bristow