Patents by Inventor Steven R. Chalmer
Steven R. Chalmer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7631143Abstract: A data storage system employs a virtual disk enclosure that utilizes a number of physical disk drives to create a set of virtual disk drives that are visible to the remainder of the storage system. The virtual disk drives exhibit a set of characteristics such as respective storage capacities, access times, and reliability measures that are user-selectable within respective limits determined by the set of corresponding physical disk drive characteristics. For example, a RAID protection scheme can be used such that the overall storage capacity of the virtual disk drives is less than that of the physical disk drives, but has greater overall reliability/availability. The system may utilize a recursive protection scheme in which the virtual disk drives are utilized according to a second RAID configuration to provide a set of highly available logical storage volumes to host computer systems connected to the data storage system.Type: GrantFiled: January 3, 2006Date of Patent: December 8, 2009Assignee: EMC CorporationInventors: Brett Niver, Steven T. McClure, Steven R. Chalmer, David L. Scheffey, Kevin E. Granlund
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Patent number: 7478202Abstract: Described is a technique for maintaining local cache coherency between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message fabric. Each processor is an endpoint having its own local cache storage in which portions of global memory may be locally cached. A write through caching technique is described. Each local cache line of data of each processor is either in an invalid or a shared state. When a write to global memory is performed by a processor (write miss or a write hit), the following are performed atomically: the global memory is updated, other processor's local cache lines of the data are invalidated, verification of invalidation is received by the processor, and the processor's local copy is updated. Other processors' cache lines are invalidated by transmission of an invalidate command by the processor. A processor updates its local cache lines upon the next read miss or write miss of the updated cacheable global memory.Type: GrantFiled: October 4, 2006Date of Patent: January 13, 2009Assignee: EMC CorporationInventors: Brett D. Niver, Steven R. Chalmer, Steven T. McClure
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Publication number: 20080162863Abstract: Managing memory includes subdividing the memory into a first set of blocks corresponding to a first size and a second set of blocks corresponding to a second size that is greater than said first size, in response to a request for an amount of memory that is less than or equal to the first size, providing one of the first set of blocks, and, in response to a request for an amount of memory that is greater than the first size and less than or equal to the second size, providing one of the second set of blocks. Subdividing the memory may also include subdividing the memory into a plurality of sets of blocks, where each particular set contains blocks corresponding to one size that is different from that of blocks not in the particular set. Each set of blocks may correspond to a size that is a multiple of a predetermined value. Managing memory may also include providing a table containing an entry for each set of blocks. The entry for each set of blocks may be a pointer to one of: an unused block and null.Type: ApplicationFiled: December 13, 2007Publication date: July 3, 2008Inventors: Steven T. McClure, Steven R. Chalmer, Brett D. Niver
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Generic reallocation function for heap reconstitution in a multi-processor shared memory environment
Patent number: 7392361Abstract: Managing memory includes receiving a request for a memory allocation, determining whether the memory allocation is to be maintained when subsequently initializing memory and saving information about the memory allocation to maintain the memory allocation during subsequently initializing memory. Initializing may be performed as part of special reset mode processing. Special reset mode processing may be performed in response to receiving a reset command. The memory may be shared by a plurality of processing units and the reset command may be issued to reset a first processing unit causing reset of the memory and a second processing unit may use a first allocated memory portion that is maintained when initializing the memory as part of processing for the reset command. Saving may include adding an entry to an allocation list associated with the memory, the entry including a location associated with the memory allocation.Type: GrantFiled: February 3, 2005Date of Patent: June 24, 2008Assignee: EMC CorporationInventors: David L. Reese, Steven R. Chalmer, Steven T. McClure, Brett D. Niver -
Patent number: 7363431Abstract: Described is a synchronization technique that may be used to coordinate processing between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message switch of the message fabric. Each processor is an endpoint within a data storage system. A first endpoint may mark the beginning of the synchronization period by specifying a processing point at which other processors and the first endpoint are to coordinate from the perspective of the first endpoint. Synchronization is performed using local state information about the processing state of each endpoint as reported by each endpoint. The first endpoint waits for successful synchronization within a timeout period in accordance with the first endpoint's local state information. If successful synchronization does not occur prior to the timeout period, the first endpoint broadcasts a message with a new synchronization point to other endpoints.Type: GrantFiled: September 19, 2003Date of Patent: April 22, 2008Assignee: EMC CorporationInventors: Brett D. Niver, Steven R. Chalmer, Steven T. McClure
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Patent number: 7343432Abstract: Described is a distributed lock processing technique that may be used to coordinate access to globally accessed resource between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message switch of the message fabric. Each processor is an endpoint within a data storage system. Each endpoint, prior to requesting a lock, dynamically determines a current lock owner of the lock to be requested in accordance with a determination of which endpoints are available as lock owners at the current time. The lock request is issued to the current lock owner with a requested time period used by the lock owner to determine an expiration time. The lock expires automatically at the expiration time even if the lock holder becomes unavailable. If the current lock owner becomes unavailable, a new lock owner is determined prior to the next request for that lock.Type: GrantFiled: September 19, 2003Date of Patent: March 11, 2008Assignee: EMC CorporationInventors: Brett D. Niver, Steven R. Chalmer, Steven T. McClure
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Patent number: 7330956Abstract: Managing memory includes subdividing the memory into a first set of blocks corresponding to a first size and a second set of blocks corresponding to a second size that is greater than said first size, in response to a request for an amount of memory that is less than or equal to the first size, providing one of the first set of blocks, and, in response to a request for an amount of memory that is greater than the first size and less than or equal to the second size, providing one of the second set of blocks. Subdividing the memory may also include subdividing the memory into a plurality of sets of blocks, where each particular set contains blocks corresponding to one size that is different from that of blocks not in the particular set. Each set of blocks may correspond to a size that is a multiple of a predetermined value. Managing memory may also include providing a table containing an entry for each set of blocks. The entry for each set of blocks may be a pointer to one of: an unused block and null.Type: GrantFiled: April 16, 2002Date of Patent: February 12, 2008Assignee: EMC CorporationInventors: Steven T. McClure, Steven R. Chalmer, Brett D. Niver
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Patent number: 7296271Abstract: Disclosed is providing one of a plurality of schedulers for a multitasking system for a processor that includes choosing a particular one of the schedulers, setting a program counter to an address corresponding to code of the particular one of the schedulers, and the processor executing code at an address corresponding to the program counter. Also included may be setting a stack pointer to an address corresponding to stack space for the particular one of the schedulers and the processor using the stack space at the stack pointer after executing code at the address corresponding to the program counter. The system described herein provides a small kernel that can run on a variety of hardware platforms, such as a PowerPC based Symmetrix adapter board used in a Symmetrix data storage device provided by EMC Corporation of Hopkinton, Ma. The core kernel code may be written for the general target platform, such as the PowerPC architecture.Type: GrantFiled: June 28, 2000Date of Patent: November 13, 2007Assignee: EMC CorporationInventors: Steven R. Chalmer, Steven T. McClure
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Patent number: 7178146Abstract: Described are techniques used in task scheduling to form a run list used by a task scheduler. A non-priority based technique is disclosed in which each task to be executed is allotted a “pie” count representing the number of times out of the total run list each task is considered for scheduling. The total run list is the sum of all the “pie” counts for all tasks. Each time a task starts, exits, or has its pie count reset, the total number of “pie” counts is computed and tasks are distributed throughout the run list. Each task is distributed in the run list in accordance with its number of “pie” counts such that a minimum number of intervening tasks appears between each successive appearance of the same task. The computed run list is then used by the scheduler. The task scheduling techniques disclosed may be used in a data storage system or elsewhere in a computer system.Type: GrantFiled: March 26, 2002Date of Patent: February 13, 2007Assignee: EMC CorporationInventors: Steven T. McClure, Steven R. Chalmer, Brett D. Niver
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Patent number: 7136969Abstract: Described is a technique for maintaining local cache coherency between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message fabric. Each processor is an endpoint having its own local cache storage in which portions of global memory may be locally cached. A write through caching technique is described. Each local cache line of data of each processor is either in an invalid or a shared state. When a write to global memory is performed by a processor (write miss or a write hit), the following are performed atomically: the global memory is updated, other processor's local cache lines of the data are invalidated, verification of invalidation is received by the processor, and the processor's local copy is updated. Other processors' cache lines are invalidated by transmission of an invalidate command by the processor. A processor updates its local cache lines upon the next read miss or write miss of the updated cacheable global memory.Type: GrantFiled: June 17, 2003Date of Patent: November 14, 2006Assignee: EMC CorporationInventors: Brett D. Niver, Steven R. Chalmer, Steven T. McClure
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Patent number: 6757790Abstract: The data storage facility includes a plurality of data storage devices coupled through multi-path connections to cache memory. A plurality of interfaces to host processors communicates with the cache memory and with cache tag controllers that define the cache memory again over multiple paths.Type: GrantFiled: February 19, 2002Date of Patent: June 29, 2004Assignee: EMC CorporationInventors: Steven R. Chalmer, Steven T. McClure, Brett D. Niver, Richard G. Wheeler
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Patent number: 6728962Abstract: Disclosed is context swapping in a multitasking operating system for a processor that includes providing a plurality of context blocks for storing context information for a plurality of processes, providing an array of pointers to the context blocks, providing an index to the array of pointers, and swapping context by adjusting at least one pointer in the array of pointers to point to a context block of a new process. Further included may be incrementing the index prior to adjusting the at least one pointer in the array of pointers. Further included may be, after adjusting at least one pointer in the array of pointers, decrementing the index and causing the processor to jump to an address indicated by a program counter value of the new process. The context information may include values for registers, a stack pointer, and a program counter for a process.Type: GrantFiled: June 28, 2000Date of Patent: April 27, 2004Assignee: EMC CorporationInventors: Steven R. Chalmer, Steven T. McClure
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Patent number: 6687903Abstract: Disclosed is inhibiting process starvation in a multitasking operating system by providing a first type of scheduling event at periodic timer intervals, providing a second type of second scheduling event in response to a running processes voluntarily relinquishing the processor, and, in response to a scheduling event, replacing an old process with a new process only if the old process has run for more than a predetermined amount of time. The predetermined amount of time may be one half of the timer interval. The system described herein provides a small kernel that can run on a variety of hardware platforms, such as a PowerPC based Symmetrix adapter board used in a Symmetrix data storage device provided by EMC Corporation of Hopkinton, Mass. The core kernel code may be written for the general target platform, such as the PowerPC architecture.Type: GrantFiled: June 28, 2000Date of Patent: February 3, 2004Assignee: EMC CorporationInventors: Steven R. Chalmer, Steven T. McClure, Brett D. Niver
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Publication number: 20030159001Abstract: The data storage facility includes a plurality of data storage devices coupled through multi-path connections to cache memory. A plurality of interfaces to host processors communicates with the cache memory and with cache tag controllers that define the cache memory again over multiple paths.Type: ApplicationFiled: February 19, 2002Publication date: August 21, 2003Inventors: Steven R. Chalmer, Steven T. McClure, Brett D. Niver, Richard G. Wheeler