Abstract: A test signal multiplexer receives supplies external test signals to a selected debug master central processing unit in a symmetrical multiprocessor system and debug slave signals to debug slave central processing units. An executive master test access port controller responds to the external test signals and controls the test signal multiplexer. A control register loadable via the executive master test access port stores the debug slave signals. A test data output multiplexer connects the test data output line of the selected debug master central processor unit to an external test data output line. The external test signals includes a debug state signal supplied to each central processing unit. This selects either a normal mode or a debug mode at each central processor unit.

Abstract: A configurable memory controller for an AMBA system is described. This configurable memory controller selects one of two possible modes of operation. The technique of configuring the memory controller provides fundamental memory control in the AMBA system while also allowing for a switching mechanism to select between the two modes, each of which entails its own set of special signal definitions. The configurable memory controller may be connected either on the AHB bus or directly connected to the ARM central processing unit core with a mechanism to switch between the two modes of operation.

Abstract: This invention is a method of complex cache memory analysis and synthesis. This invention proceeds in the normal fashion of writing a program and simulating it, but makes use of a closed loop design approach to completing the analysis-synthesis process. A program behavior analysis tool PBAT is integrated as part of an otherwise conventional program development tool. The PBAT offers a single environment where code development, simulator trace capture, and cache analysis take place. The cache analysis tool of PBAT is designed to match the current cache design of the processor and to identify any weakness in the current design or special features that need to be added. Code adjustments are passed back to the assembler and linker and in successive simulations using the integrated PBAT tool resulting in code that better fits a specific cache design.

Abstract: A single chip, embedded symmetric multiprocessor (ESMP) having parallel multiprocessing architecture composed of identical processors allows application developers to write code for a single processor case. This code can be ported to a multiprocessor platform with minimal changes. The application boot or kernel code must be modified to support the parallel processing platform. However, the hardware architecture allows the program stream, at the application task or process level, to be divided among different central processing units without change to the application code. The embedded symmetric processor system includes central processing units, complex memory architectures and a wide range of peripheral devices on the single integrated circuit. Such a system normally also includes an interface to large amounts of external memory. Special hardware manages central processing unit interactions with program memory, data memory and peripherals.

Abstract: In multiprocessor systems the task of holding power dissipation to its lowest possible level is challenging. This invention permits reduced power dissipation by optionally clocking selected central processing units at lower frequencies if they are not fully loaded. The variable clocking system enables synchronization between central processing units operating a differing frequencies and shared memory and peripherals. This allows for significant power reduction in the frequently occurring scenario where all processors are not driven to their limits by prevailing system requirements.

Abstract: In an embedded symmetric multiprocessor (ESMP) system it is desirable to maintain equal central processing unit load balance. When an interrupt occurs, a single central processing receives the interrupt and then passes information to the central processing unit scheduling software. This software will in turn determine which central processing unit can best handle the interrupt. Because the scheduling software is able to determine which central processing unit handles the interrupt process, it can maintain central processing unit load balancing resulting in better system performance.

Abstract: A micro-controller direct memory access (DMA) unit includes hardware support for single read of the source address at a source word size and but writes to the target address at an independent target word size. This permits, for example, a single read of the source address at a larger word size and multiple sub-word sized writes to the target address. This is enabled by independent control register storage of a source word size, a source increment size, a target word size and a target increment size. A byte shifter/register that will shifts a full byte at a time to the next lower byte position allowing transfer of a large word to a destination having a small word size.

Abstract: A bus bridge is defined to provide an interface between two AHB buses. These busses normally have separate requirements but both must provide high performance. The first is for transfer of data from CPU to memory and peripherals. The second is to support the transfer of a large amount of data by a single peripheral to local memory or other local peripherals. The AHB-to-HTB bus bridge provides a means for the interfacing these two separate AHB buses allowing communication between them and securing data integrity. The bus bridge of this invention is defined to be an AHB memory bus slave but a high performance data transfer bus master.

Abstract: This invention comprises a multiple transaction advanced high performance bus AHB system using two separate fully autonomous AHB buses, each having its own bus arbitration system with decoding to allow for simultaneous activity on the two AHB buses. The two buses are separated by and synchronized with an AHB-to-HTB bus bridge. The first bus, the Memory Bus AHB, contains the CPU and DMA as bus masters and the external memory controller and internal memory as slaves. The second bus, the Data Transfer Bus HTB, contains the high performance peripheral and any local RAM required.

Abstract: The time-out counter of this invention provides a capability in a bus bridge for a first bus master to generate a time-out interrupt if it is not given control of the second bus within a certain time period when the time of arbitration on the second bus is excessive. The time-out counter is programmable up to 16-bits and allowing the software selection of the time-out length. This time-out feature is useful if the manner of arbitration used would otherwise allow the second bus master to have absolute control of the first bus.

Abstract: The problem of the turn signal inadvertently remaining on is solved through the use of additional intelligence added on to the current turn-signal control system already existing within current late-model vehicles. The turn-control circuitry in a vehicle first sends a signal to the ABS system indicating to the ABS system that the turn signal has been turned on. The amount of distance traveled from a certain event, such as when the turn signal is turned on, can be ascertained by the ABS system, as distance traveled for odometer purposes has always been a product of the ABS system. Therefore, when a predetermined distance has passed since the turn signal was activated, the ABS system, sends a signal back to the turn-control circuitry, instructing the turn-control circuitry to turn off the turn signal.