Abstract: An electronic circuit for simultaneously erasing all the information stored in an electronic information storage device and entering a predetermined new pattern of information into the storage device comprises a plurality of bistable semiconductor cells with an additional transistor current-conducting region included on a predetermined side of each cell. The additional current-conducting regions in the cells along each word row are coupled to an additional word line which connects to a current switch for the row. At an appropriate pulse signal, the current switch activates to switch row current temporarily from the standard current-source word line, which conducts holding current to the row during normal operation, to the additional word line, thereby erasing the old data and entering the new information bits.