Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for receiving a user-level instruction for a checksum operation in a processor, where the user-level instruction specifies a source operand of a first size and a destination operand of a second size, receiving the source operand and the destination operand in the processor, and performing the checksum operation using the source operand and the destination operand in the processor responsive to the instruction. In an embodiment, the processor has multiple hardware engines that each can perform the checksum operation for one of multiple data sizes. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for determining from a data block in a buffer a number of first operands in a first portion of the buffer and a number of second operands in a second portion of the buffer. Based on these numbers, a cyclic redundancy checksum (CRC) operation may be iteratively performed on the first and second operands to obtain a checksum result. The first and second operands are of a different length, and the checksum operation may be executed using processor instructions corresponding to the different lengths. Other embodiments are described and claimed.

Abstract: In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.

Abstract: In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: Techniques for performing direct memory access (“DMA”) in an architecture wherein an interconnect separates I/O means from a DMA engine for handling DMA requests of the I/O means. In an embodiment, the I/O means sends via the interconnect a DMA request including an address-non-specific identifier of a queue which is a target of the DMA request. In another embodiment, the DMA engine determines an address-specific identifier of a location in the queue in response to the sending of the DMA request.

Abstract: In one embodiment, the present invention includes a method for determining from a data block in a buffer a number of first operands in a first portion of the buffer and a number of second operands in a second portion of the buffer. Based on these numbers, a cyclic redundancy checksum (CRC) operation may be iteratively performed on the first and second operands to obtain a checksum result. The first and second operands are of a different length, and the checksum operation may be executed using processor instructions corresponding to the different lengths. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for determining from a data block in a buffer a number of first operands in a first portion of the buffer and a number of second operands in a second portion of the buffer. Based on these numbers, a cyclic redundancy checksum (CRC) operation may be iteratively performed on the first and second operands to obtain a checksum result. The first and second operands are of a different length, and the checksum operation may be executed using processor instructions corresponding to the different lengths. Other embodiments are described and claimed.

Abstract: In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.

Abstract: Techniques to indicate whether datum transferred from a memory device to a second device is likely to be accessed again by the second device. The second device may include a buffer memory to store the datum when the datum is indicated as likely to be accessed again. If the second device is to access the datum again after receipt from the memory device, the second device may retrieve the datum from the buffer memory instead of from the memory device. Accordingly, multiple accessed of datum transferred once from an external memory are possible.

Abstract: A system and method for processing a packet such as an inbound RDMA write packet in a network communication system. When processing the packet, a prefetch may retrieve a header of the next packet or, in the case of the inbound RDMA write packet, the prefetch may additionally retrieve an inbound RDMA send context. Subsequent to the prefetch beginning, processing of the packet may be completed and much of the overhead for processing of the next packet may have already completed. Other embodiments are also described.

Abstract: Techniques are described herein that may utilize capabilities of a data mover in order to determine an integrity validation value or perform an integrity checking operation. The integrity validation value determination and integrity checking operations may be controlled by descriptors or instructions. In some implementations, integrity validation value determination and the integrity checking operations may include determination of a cyclical redundancy checking (CRC) value.

Abstract: In general, in one aspect, a computer-implemented method includes determining a digest value based on hash operations on values of, at least, a set op-codes of multiple instructions of a program during execution of the program by a processor.

Abstract: A system, method, and apparatus are provided for external device-based prefetching mechanism. According to one embodiment, a packet is received at a network interface card in communication with a host computer system and a network. The packet is received from the network and includes a context as indicated by a packet address. Then, lookup in packet context table is performed. If a match is found, the received packet is associated with host memory addresses that are sent by the NIC to the processor as prefetch directives. The packet is then forwarded to the host computer system.

Abstract: A method, system, computer program product, and expansion card capable of: defining an initial source address within a source memory device. An initial data read operation is performed to retrieve a first X-byte data portion from the source memory device. The initial data read operation begins at the initial source address. The initial source address is incremented by Y bytes to define a secondary source address within the source memory device, such that Y is greater than X.

Abstract: Methods, apparatuses, articles, and systems for facilitating network-like communication between two processes of two different virtual machines of a plurality of virtual machines operating on a common platform or physical device are described herein. In various embodiments, the physical device includes at least one sharable memory page to host an inter-domain staging buffer, and each virtual machine may include an instantiation of an inter-domain buffer manager, a data mover, an event manager and/or an inter-domain networking interface.

Abstract: This invention is directed to an apparatus and method for providing improved control of fuel, preferably gaseous fuel, to an internal combustion engine such that each cylinder of the engine will operate within a predetermined tolerance off of its lean misfire limit. The disclosed system introduces fuel to the engine at two locations: (1) upstream of the intake manifold to provide premixing of a majority of the fuel with air, and (2) near the intake valve of each cylinder for tailoring the fuel flow to each cylinder to achieve that fuel-to-air ratio which is necessary to maintain each cylinder at the desired tolerance from the lean misfire limit. Several calibration and control methods are described to maximize performance of the fuel system, including the use of a misfire detection technique to determine the lean misfire limit of each cylinder to allow the respective port fuel injector to provide a specified margin from lean misfire.

Abstract: A multipoint fuel delivery system for an internal combustion engine includes fuel metering device(s) such as fuel injector(s) associated for selectively controlled injection of the second fuel to corresponding combustion chamber(s) of the internal combustion engine. A fuel supply manifold associates with fuel injector(s) for directing the second fuel to each fuel injector. An intake port adaptor mechanism adapts the intake port of the associated combustion chamber to receive the selectively controlled injection of the fuel from an associated fuel injector. The intake port adaptor mechanism may also engage the intake port so as to permit selective flow of the first fuel or the second fuel to the intake port of the selected combustion chamber. A control mechanism selectively controls the flow of the second fuel through each injector(s).