Abstract: A technique for observing signaling on the traces between ICs on a PC board without introducing significant signal degradation is provided. A route-through connector footprint allows the use of a standard connector without the use of stub traces. The route-through connector footprint allows a standard connector to be introduced directly into the line traces routed between ICs. Because stub traces are not used, this technique for mechanical interconnection into the line traces on a PC board allows for a single board layout to be used for both test and production. Additionally, because stub traces are not used, signal quality is minimally impacted and testing can be performed at operational speeds improving the reliability of the test function. The use of a route-through connector footprint additionally saves PC board space and cost.

Abstract: A split-transaction bus decoder receives a plurality of packets, the plurality of packets including a request packet and a response packet, wherein the request packet includes an address and a request tag; and the response packet includes a command, a response tag, and data. Upon receipt of the request packet, the decoder stores the address and the request tag. Upon receipt of the response packet, the decoder matches the response tag to the request tag. The decoder produces a decoded packet including the address of the request packet and the command and the data of the response packet.

Abstract: An improved split-transaction bus intelligent logic analysis tool has a bus synchronizer, a decoder and a logic analysis function. The bus synchronizer is configured to receive link traffic and frame the link traffic into a plurality of framed packets, the plurality of framed packets including a plurality of request packets and a plurality of response packets. The decoder is configured to receive the plurality of framed packets and decode the plurality of framed packets into decoded packets, wherein at least one of the decoded packets includes information from a request packet and information from a corresponding response packet. The logic analysis function is configured to receive the decoded packets and initiate a trigger action on receipt of one of the decoded packets.

Abstract: An apparatus and method are presented for monitoring the performance of a microprocessor. The apparatus includes performance monitoring hardware incorporated within the microprocessor. The performance monitoring hardware includes a memory unit for storing performance data. The memory unit includes multiple memory locations, each memory location being accessed by a unique set of address signals. Circuitry within the performance monitoring hardware produces the address signals. In one embodiment, the performance monitoring hardware includes an event select register array and circuitry for producing a set of high order (i.e., most significant) address signals. The event select register array preferably includes several event select registers for storing binary codes corresponding to selected events. A performance data acquisition period is divided into multiple histogram time periods of equal length. The high order address signals partition the memory unit into sections.

Abstract: An apparatus and method are presented for monitoring the performance of a microprocessor. The apparatus includes performance monitoring hardware incorporated within the microprocessor. The performance monitoring hardware includes a memory unit for storing performance data. The memory unit includes multiple memory locations, each memory location being accessed by a unique set of address signals. Circuitry within the performance monitoring hardware produces the address signals. In one embodiment, the performance monitoring hardware includes an event select register array and circuitry for producing a set of high order (i.e., most significant) address signals. The event select register array preferably includes several event select registers for storing binary codes corresponding to selected events. A performance data acquisition period is divided into multiple histogram time periods of equal length. The high order address signals partition the memory unit into sections.