Patents by Inventor Steven R. Loza

Steven R. Loza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for testing chip-on-glass bonding quality
    Patent number: 9928767
    Abstract: A system and method of testing chip-on-glass (COG) bonding quality automatically includes a glass panel comprising two test pads, the test pads electrically interconnected, a display driver comprising an input node and an output node, and an adhesive layer between the glass panel and the display driver, the adhesive layer binding the glass panel with the display driver, the adhesive layer comprising conductive portions across the adhesive layer between the glass panel and the display driver, wherein the input node, the output node, the two test pads, and the conductive portions are electrically connected to form an electrical testing loop, the electrical testing loop configured to measure a voltage drop across the conductive portions.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: March 27, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Xiangan Zhu, Guoping Luo, Qian Han, Shunlin Chen, Guangrong Wu, Jose Garcia, Steven R. Loza, Chuanning Chen
  • System and Method for Testing Chip-on-Glass Bonding Quality
    Publication number: 20170193870
    Abstract: A system and method of testing chip-on-glass (COG) bonding quality automatically includes a glass panel comprising two test pads, the test pads electrically interconnected, a display driver comprising an input node and an output node, and an adhesive layer between the glass panel and the display driver, the adhesive layer binding the glass panel with the display driver, the adhesive layer comprising conductive portions across the adhesive layer between the glass panel and the display driver, wherein the input node, the output node, the two test pads, and the conductive portions are electrically connected to form an electrical testing loop, the electrical testing loop configured to measure a voltage drop across the conductive portions.
    Type: Application
    Filed: January 5, 2016
    Publication date: July 6, 2017
    Inventors: Xiangan Zhu, Guoping Luo, Qian Han, Shunlin Chen, Guangrong Wu, Jose Garcia, Steven R. Loza, Chuanning Chen