Abstract: A variable tracking word recognizer generates an indicating signal when a microprocessor has accessed a memory stack location storing a dynamically addressed variable, the address of the variable being the sum of a dynamically assigned base address of the memory stack and a known address offset where the variable is stored on the stack in relation to the base address. The variable tracking word recognizer stores the dynamically assigned base address, when determined by a space allocation subroutine of a program running on the microprocessor, and then monitors the addresses subsequently appearing on the microprocessor address bus, generating the indicating signal when the current address matches the combination of stored base address and known address offset.

Abstract: A detector circuit for detecting skew or phase shift of at least three logic signals comprises an OR gate for receiving a plurality of logic signals, an exclusive-OR gate for receiving an output signal from the OR gate as well as a reference logic signal, and a pulse width check circuit responsive to the exclusive-OR gate for providing the skew detection result.

Abstract: An apparatus for time aligning data acquired by one test instrument with corresponding data acquired by another test instrument is disclosed. A set of binary codes, representative of a set of instructions executed by a microprocessor disposed within a user's prototype circuit, are acquired by said one test instrument. With the acquisition of each of said binary codes, a count is developed in a counter indicative of each said acquisition. A multitude of binary data is acquired, independently of the acquisition of the set of binary codes, by said another test instrument, the multitude of binary data being representative of the functions performed by a set of components present within said user's prototype circuit. The binary codes acquired by said one test instrument and the binary data acquired by said another test instrument each have associated therewith a count developed from said counter.

Abstract: An input apparatus for a multi-channel device, such as a logic analyzer, is disclosed, the input apparatus providing the multi-channel device with a programmable set-up and hold feature. The multi-channel device acquires a logic signal from a product under test, the logic signal having associated therewith an actual set-up and hold time with respect to an external clock signal. The actual set-up and hold times are entered into the multi-channel device via a keyboard and a display. The device has stored therein a desired set-up and hold time required by the logic signal relative to the external clock signal. In accordance with the actual and the desired set-up and hold times, the multi-channel device changes the relative orientation of the acquired logic signal with respect to the external clock signal, along the time axis until the set-up and hold times of the acquired logic signal are changed from the actual value to the desired value.

Abstract: A method and apparatus for establishing the correct order of probe channels in a logic analyzer is disclosed. Logic analyzers have probe PODS connected thereto, the PODS having a plurality of probe tips connected thereto for further connection to the terminals of a product under test. With this invention, the order of connection of the tips to the terminals can be ignored because the correct order is established via the logic analyzer (LA) itself. A ROM has firmware stored therein for enabling the logic analyzer to establish the correct order of connection. The binary data from each POD is stored in memory. The binary data in memory may be converted to hexadecimal form and stored in the display controller. By using a keyboard, the operator displays, on the LA display, a menu-mode display, which includes a display of the probe channel identifiers for each POD, the identifiers reflecting the actual order of connection of the probe tips to the terminals of the product under test.

Abstract: An input apparatus for a logic analyzer is disclosed which receives a plurality of logic signals from a probe, the plurality of logic signals being received at different points in time, the input apparatus being capable of generating a corresponding plurality of logic signals in response thereto, the time of generation of the corresponding plurality of logic signals substantially coinciding with the time of generation of a corresponding reference logic signal. The input apparatus comprises a plurality of tapped delay lines corresponding to the plurality of received logic signals. A controller controls the amount of time delay for each delay line associated with each received logic signal. The controller continues this control function until the time of generation of the corresponding plurality of logic signals substantially coincides with the time of generation of the corresponding reference logic signal.

Abstract: A logic analyzer for measuring individually a plurality of logic signals transmitted via a multiplexed digital bus in a time-sharing manner is disclosed. First and second memory circuits store respectively first and second logic signals of the multiplexed digital bus in accordance with first and second strobe signals synchronized with the first and second logic signals.

Abstract: A logic analyzer which can simultaneously measure one block of input data in detail and the same or another block of input data in rough form is disclosed. The logic analyzer comprises first and second sections each including a memory circuit to store the input data and a word recognizer to detect the desired trigger word from the input data. These first and second sections receive different clocks having different rates, and the second memory circuit stores the first clock applied to said first section for recognizing the time relationship of these clock signals. A counter counts the first clock in accordance with the outputs from the first and second word recognizers for recognizing the time relationship of the first and second trigger words.

Abstract: A programmable pulse generator which generates a pulse having programmable leading and trailing edges is disclosed. An oscillator starts to generate a pulse in response to a trigger signal, and the pulse is counted by a counter for generating an address signal. A memory circuit generates a pulse having predetermined time occurrence of leading and trailing edges in accordance with the address signal, and the transition detector detects the trailing edge to stop the oscillation of the oscillator.