Abstract: A system and method for using an embedded microprocessor in an RF amplifier. The use of an embedded microprocessor avoids manual calibration. The Microprocessor collects initial amplifier performance data based on a set of parameters and calculates the needed corrections. The microprocessor can change levels within the circuit to achieve those operating points. The embedded microprocessor sets voltage levels with internal circuitry and communicates this information externally through a serial communication port, or the like, to allow a user to communicate with and look at the amplifier data and readjust the internal bias levels, as needed. Thus, the internal microprocessor provides for calibration, self-testing, and monitoring of the RF amplifier and also functions as an in situ bias and temperature compensation controller for use in the presence of temperature variation and provides bias sequencing control to protect against improper applied timing of voltage inputs to the amplifier.

Abstract: A system and method for using an embedded microprocessor in an RF amplifier. The use of an embedded microprocessor avoids manual calibration. The Microprocessor collects initial amplifier performance data based on a set of parameters and calculates the needed corrections. The microprocessor can change levels within the circuit to achieve those operating points. The embedded microprocessor sets voltage levels with internal circuitry and communicates this information externally through a serial communication port, or the like, to allow a user to communicate with and look at the amplifier data and readjust the internal bias levels, as needed. Thus, the internal microprocessor provides for calibration, self-testing, and monitoring of the RF amplifier and also functions as an in situ bias and temperature compensation controller for use in the presence of temperature variation and provides bias sequencing control to protect against improper applied timing of voltage inputs to the amplifier.

Abstract: Techniques and architecture are disclosed for providing an ultra-wideband, multi-channel solid-state power amplifier architecture. In some embodiments, the architecture includes a power divider which splits an input signal and delivers that split signal to a plurality of downstream channel chipsets. Each channel chipset is configured to amplify a sub-band of the original full-band input signal and to provide the resultant amplified sub-band for downstream use, such as for transmission by an antenna operatively coupled with that channel. In the aggregate, the amplified sub-bands provide coverage of the same ultra-wideband frequency range of the original input signal, in some cases. In some embodiments, the architecture provides high radio frequency (RF) power with good amplifying efficiency and ultra-wide instantaneous frequency bandwidth performance in a small-form-factor package.