Patents by Inventor Steven Reinhardt

Steven Reinhardt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10669566
    Abstract: A system for automated microorganism identification and antibiotic susceptibility testing comprising a reagent cartridge, a reagent stage, a cassette, a cassette, stage, a pipettor assembly, an optical detection system, and a controller is disclosed. The system is designed to dynamically adjust motor idle torque to control heat load and employs a fast focus process for determining the true focus position of an individual microorganism. The system also may quantify the relative abundance of viable microorganisms in a sample using dynamic dilution, and facilitate growth of microorganisms in customized media for rapid, accurate antimicrobial susceptibility testing.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: June 2, 2020
    Assignee: Accelerate Giagnostics, Inc.
    Inventors: William L. Richards, Austin Ashby, Matthew Ketterer, Kevin Marshall, Josh Harrison, Matthew Mette, Paul Richards, Wayne Showalter, Jasmin Cote, Steven W. Metzger, Ken Hance, Meghan Mensack, Carlos Michel, Elke Allers, Dulini Gamage, Landon Prisbrey, Oleg Gusyatin, Alena Shamsheyeva, Ben Turng, Andrew Ghusson, Kurt Reinhardt, Phillip C. Halbert, Solene Bourgeois
  • Patent number: 9626428
    Abstract: A system and method for accessing a hash table are provided. A hash table includes buckets where each bucket includes multiple chains. When a single instruction multiple data (SIMD) processor receives a group of threads configured to execute a key look-up instruction that accesses an element in the hash table, the threads executing on the SIMD processor identify a bucket that stores a key in the key look-up instruction. Once identified, the threads in the group traverse the multiple chains in the bucket, such that the elements at a chain level in the multiple chains are traversed in parallel. The traversal continues until a key look-up succeeds or fails.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: April 18, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mithuna Thottethodi, Steven Reinhardt
  • Publication number: 20150074372
    Abstract: A system and method for accessing a hash table are provided. A hash table includes buckets where each bucket includes multiple chains. When a single instruction multiple data (SIMD) processor receives a group of threads configured to execute a key look-up instruction that accesses an element in the hash table, the threads executing on the SIMD processor identify a bucket that stores a key in the key look-up instruction. Once identified, the threads in the group traverse the multiple chains in the bucket, such that the elements at a chain level in the multiple chains are traversed in parallel. The traversal continues until a key look-up succeeds or fails.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 12, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Mithuna THOTTETHODI, Steven Reinhardt
  • Publication number: 20060095821
    Abstract: A method and apparatus for a checker instruction in a redundant multithreading environment is described. In one embodiment, when RMT requires, a processor may issue a checker instruction in both a leading thread and a trailing thread. The checker instruction may travel down individual pipelines for each thread independently until it reaches a buffer at the end of each pipeline. Then, prior to committing the checker instruction, the checker instruction looks for its counterpart and does a comparison of the instructions. If the checker instructions match, the checker instructions commit and retires otherwise an error is declared.
    Type: Application
    Filed: September 29, 2004
    Publication date: May 4, 2006
    Inventors: Shubhendu Mukherjee, Joel Emer, Steven Reinhardt, Christopher Weaver
  • Publication number: 20050283685
    Abstract: A technique to reduce false error detection in microprocessors by tracking instructions neutral to errors. As an instruction is decoded, an anti-pi bit is tagged to the decoded instruction. When a parity error is detected, an instruction queue first checks if the anti-pi bit is set. If the anti-pi bit is set, then instruction is neutral to errors, and the pi bit need not be set. Prefetch, branch predict hint and NOP are types of instructions that are neutral to errors.
    Type: Application
    Filed: June 17, 2004
    Publication date: December 22, 2005
    Inventors: Joel Emer, Shubhendu Mukherjee, Steven Reinhardt, Christopher Weaver
  • Publication number: 20050283716
    Abstract: A technique to reduce false error detection in microprocessors. A pi bit is propagated with an instruction through an instruction flow path. When a parity error is detected, the pi bit is set, instead of raising a machine check exception. Upon reaching a commit point, the processor can determine if the instruction was on a wrong path.
    Type: Application
    Filed: June 17, 2004
    Publication date: December 22, 2005
    Inventors: Shubhendu Mukherjee, Joel Emer, Steven Reinhardt, Christopher Weaver, Michael Smith
  • Publication number: 20050283590
    Abstract: A technique to reduce false error detection in microprocessors by tracking dynamically dead instructions. When an instruction commits, it is then stored in a PET buffer. A processor may now declare a machine check error when the instruction is being removed from the PET buffer rather than at the commit point. The processor can scan the PET buffer to determine if the instruction is a dynamically dead instruction. This further enables the processor to reduce false positives.
    Type: Application
    Filed: June 17, 2004
    Publication date: December 22, 2005
    Inventors: Christopher Weaver, Shubhendu Mukherjee, Joel Emer, Steven Reinhardt
  • Publication number: 20050283712
    Abstract: A technique to reduce false error detection in microprocessors within a redundant multi-threaded computing environment. A pi bit is propagated with at least two instructions through an instruction flow path. Results of executing the instruction are compared to see if an error has occurred and if so, the pi bits are examined to determine which instruction contains the error.
    Type: Application
    Filed: September 22, 2004
    Publication date: December 22, 2005
    Inventors: Shubhendu Mukherjee, Joel Emer, Steven Reinhardt, Christopher Weaver, Michael Smith
  • Publication number: 20050193283
    Abstract: A multithreaded architecture is disclosed for buffering unchecked stores for fault detection in redundant multithreading systems using speculative memory support. In particular, the performance of a SRT processor is enhanced by using speculative memory support to buffer the leading threads stores until they can be compared with their trailing thread counterparts. Buffering these stores in the memory system allows them to be removed from the store buffer. Since the speculative memory system will have greater capacity than the store buffer, additional stores may be buffered before the leading thread will be forced to stall. This will result in an increase in slack between threads, and thus an increase in performance.
    Type: Application
    Filed: December 30, 2003
    Publication date: September 1, 2005
    Inventors: Steven Reinhardt, Shubhendu Mukherjee, Joel Emer, Christopher Weaver
  • Publication number: 20050154944
    Abstract: A multithreaded architecture is disclosed for managing external memory updates for fault detection in redundant multithreading systems using speculative memory support. In particular, a method provides input replication of load values on a SRT processor by using speculative memory support to isolate redundant threads form external updates. This method thus avoids the need for dedicated structures to provide input replication.
    Type: Application
    Filed: December 30, 2003
    Publication date: July 14, 2005
    Inventors: Steven Reinhardt, Shubhendu Mukherjee, Joel Emer, Christopher Weaver
  • Publication number: 20050050304
    Abstract: Methods and apparatuses for incremental, periodic storage of checkpoints in a multi-threaded processor.
    Type: Application
    Filed: August 29, 2003
    Publication date: March 3, 2005
    Inventors: Shubhendu Mukherjee, Steven Reinhardt, Joel Emer
  • Publication number: 20050050386
    Abstract: Log-based hardware recovery. A checkpointed state of a system includes both architectural register values and memory. The checkpoint consists of a copy of the architectural register file values at the time the checkpoint is generated. An ordered log of non-deterministic events is maintained so that the responses can be repeated to simulate a complete checkpoint for error recovery purposes. When a processor detects an error, the processor reloads the state from the last checkpoint and repeats the non-deterministic events from the log.
    Type: Application
    Filed: August 29, 2003
    Publication date: March 3, 2005
    Inventors: Steven Reinhardt, Shubhendu Mukherjee, Joel Emer
  • Publication number: 20050050307
    Abstract: A multithreaded architecture having one or more checker circuits that operate on store operations that send data outside of a sphere of replication. Fault detection mechanisms used to check outputs from the sphere of replication are reused for checkpointing at the conclusion of an execution epoch.
    Type: Application
    Filed: August 29, 2003
    Publication date: March 3, 2005
    Inventors: Steven Reinhardt, Shubhendu Mukherjee, Joel Emer
  • Patent number: 6536461
    Abstract: A subsea pig launching apparatus for launching one or more pigs into a flowline which is fluidly connectable to a source of well fluid comprises at least one first hub to which the source of well fluid is connectable and which is in communication with the flowline, a first valve which is positioned between the first hub and the flowline, a second hub which is in communication with the flowline, and a pig launcher which is removably connectable to the second hub and which comprises at least one pig, at least one launch valve which is positioned between a pressure source and the pig, and a launch actuator for selectively opening and closing the launch valve. The launch actuator is controlled by a signal which is communicated through at least one of a number of external control and service lines that are connected to a control and service umbilical for the source of well fluid.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: March 25, 2003
    Assignee: FMC Technologies, Inc.
    Inventors: Robert R. Decker, Harold B. Skeels, Steven A. Reinhardt
  • Publication number: 20020117208
    Abstract: A subsea pig launching apparatus for launching one or more pigs into a flowline which is fluidly connectable to a source of well fluid comprises at least one first hub to which the source of well fluid is connectable and which is in communication with the flowline, a first valve which is positioned between the first hub and the flowline, a second hub which is in communication with the flowline, and a pig launcher which is removably connectable to the second hub and which comprises at least one pig, at least one launch valve which is positioned between a pressure source and the pig, and a launch actuator for selectively opening and closing the launch valve. The launch actuator is controlled by a signal which is communicated through at least one of a number of external control and service lines that are connected to a control and service umbilical for the source of well fluid.
    Type: Application
    Filed: February 21, 2002
    Publication date: August 29, 2002
    Inventors: Robert R. Decker, Harold B. Skeels, Steven A. Reinhardt