Abstract: Embodiments of the present disclosure provide an apparatus including: a controller communicatively coupled to a power generation system and configured to shift the power generation system between a first operating mode and a second operating mode, the second operating mode being different from the first operating mode; and a economic optimization engine in communication with the controller, wherein the economic optimization engine calculates: an economic benefit for shifting the power generation system from the first operating mode to the second operating mode based on at least one of a power generation demand, a power generation cost, and an operating condition of the power generation system; and a billing rate per unit of time of operation in the second operating mode based on at least one of the economic benefit, an operating difference between the first operating mode and the second operating mode, and a predetermined cost differential.

Abstract: Embodiments of the present disclosure provide an apparatus including: a controller communicatively coupled to a power generation system and configured to shift the power generation system between a first operating mode and a second operating mode, the second operating mode being different from the first operating mode; and a economic optimization engine in communication with the controller, wherein the economic optimization engine calculates: an economic benefit for shifting the power generation system from the first operating mode to the second operating mode based on at least one of a power generation demand, a power generation cost, and an operating condition of the power generation system; and a billing rate per unit of time of operation in the second operating mode based on at least one of the economic benefit, an operating difference between the first operating mode and the second operating mode, and a predetermined cost differential.

Abstract: A method and apparatus are disclosed for adjusting the individual data hold time of data output buffers. Clock signals for the output buffers are respectively and individually adjusted for each of the output buffers to ensure a desired timing relationship among all of the data output by the buffers.

Abstract: An apparatus, system and method for identifying an access mode of a semiconductor memory in a data processing system, characterized by significant reduction of the possibility of erroneous identification of the access mode. A semiconductor memory has an access circuit bank with plurality of selectable circuits only one of which is activated, each selectable circuit respectively associated with a selectable semiconductor memory access mode, the access mode selection typically being accomplished by selectively blowing fuses associated with the corresponding selectable circuits. A semiconductor memory access mode is correctly identified by associating, in response to a test signal for determining the fuse status, the respective activated selectable circuit with its corresponding access mode.