Patents by Inventor Steven Richard Ethridge

Steven Richard Ethridge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230171898
    Abstract: Back drilling vias of a PCB, including: identifying a particular diameter of a particular via of multiple vias of the PCB; back drilling of the particular via with a first drill bit having a first diameter, the first diameter a first percentage greater than the particular diameter of the particular via; determining whether the first diameter of the first drill bit is a threshold percentage greater than the particular diameter of the particular via; determining that the first diameter of the first drill bit is less than the threshold percentage greater than the particular diameter of the particular via, and in response: back drilling of the particular via with a second drill bit having a second diameter, the second diameter a second percentage greater than the particular diameter of the particular via, the second diameter greater than the first diameter.
    Type: Application
    Filed: December 1, 2021
    Publication date: June 1, 2023
    Inventors: Steven Richard Ethridge, Ching-Huei Chen, Bhyrav M. Mutnury
  • Patent number: 10856411
    Abstract: A printed circuit board (PCB) includes a plurality of layers and electronic components connected to its top surface. The PCB also includes a plurality of trace layers, each located at a respective depth within the layers of the PCB. A plurality of vias provide signal pathways for the trace layer. Upon their manufacture, the vias include a stub portion not necessary for the signal pathways and causing degradation of the integrity of these signal pathways. Embodiments mill the bottom of the PCB to form a variable-depth cavity. The different milling depths of the variable-depth cavity are selected to remove the stub portions of the plurality of vias and the dielectric material between the stubs. By configuring the PCB power planes as the topmost trace layers, decoupling capacitors may be located at the greatest depth of the variable-depth cavity, thus reducing the loop inductance in the power circuit of the PCB.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 1, 2020
    Assignee: Dell Products, L.P.
    Inventors: Sandor Farkas, Bhyrav M. Mutnury, Steven Richard Ethridge
  • Publication number: 20200008296
    Abstract: A printed circuit board (PCB) includes a plurality of layers and electronic components connected to its top surface. The PCB also includes a plurality of trace layers, each located at a respective depth within the layers of the PCB. A plurality of vias provide signal pathways for the trace layer. Upon their manufacture, the vias include a stub portion not necessary for the signal pathways and causing degradation of the integrity of these signal pathways. Embodiments mill the bottom of the PCB to form a variable-depth cavity. The different milling depths of the variable-depth cavity are selected to remove the stub portions of the plurality of vias and the dielectric material between the stubs. By configuring the PCB power planes as the topmost trace layers, decoupling capacitors may be located at the greatest depth of the variable-depth cavity, thus reducing the loop inductance in the power circuit of the PCB.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: Dell Products, L.P.
    Inventors: Sandor Farkas, Bhyrav M. Mutnury, Steven Richard Ethridge