Abstract: In a digital system with a processor coupled to a paged memory system, the memory system may be dynamically configured using a memory compaction manager in order to allow portions of the memory to be placed in a low power mode. As applications are executed by the processor, program instructions are copied from a non-volatile memory coupled to the processor into pages of the paged memory system under control of an operating system. Pages in the paged memory system that are not being used by the processor are periodically identified. The paged memory system is compacted by copying pages that are being used by the processor from a second region of the paged memory into a first region of the paged memory. The second region may be placed in a low power mode when it contains no pages that are being used by the processor.

Abstract: In a digital system with a processor coupled to a paged memory system, the memory system may be dynamically configured using a memory compaction manager in order to allow portions of the memory to be placed in a low power mode. As applications are executed by the processor, program instructions are copied from a non-volatile memory coupled to the processor into pages of the paged memory system under control of an operating system. Pages in the paged memory system that are not being used by the processor are periodically identified. The paged memory system is compacted by copying pages that are being used by the processor from a second region of the paged memory into a first region of the paged memory. The second region may be placed in a low power mode when it contains no pages that are being used by the processor.

Abstract: Methods and apparatus to provide refresh for local out of range read requests for a memory device are disclosed. An example method disclosed herein provides a read signal to a memory cell. An address is received on row address lines ranging from a most significant bit row address line to a least significant bit row address line. A fixed high logic input is coupled to a first input of a row driver logic device associated with a local out of range address. Logic is provided to send a read enable signal on a bit line coupled to an output of the row driver logic device coupled to the memory cell if the address is the local out of range address.

Abstract: Methods and apparatus to provide refresh for local out of range read requests for a memory device are disclosed. An example method disclosed herein provides a read signal to a memory cell. An address is received on row address lines ranging from a most significant bit row address line to a least significant bit row address line. A fixed high logic input is coupled to a first input of a row driver logic device associated with a local out of range address. Logic is provided to send a read enable signal on a bit line coupled to an output of the row driver logic device coupled to the memory cell if the address is the local out of range address.