Patents by Inventor Steven S. Cooperman

Steven S. Cooperman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5494857
    Abstract: A new method for planarization of shallow trenches is presented. Shallow trenches are patterned into a semiconductor substrate that has been coated with a layer of silicon nitride. A conformal coating of oxide is deposited onto the wafer to fill the trenches. A thin layer of etch-stop silicon and a second layer of oxide are then deposited. The second layer of oxide is patterned with a filler mask using conventional photolithographic techniques and etched to the silicon etch-stop layer, leaving blocks of oxide in the depressions above the trenches and oxide spacers along the sidewalls. Chemical mechanical polishing is then used to polish the oxide back to the silicon nitride. The process offers excellent global planarity, minimal variation in silicon nitride thickness across active areas of varying size and density, and relative insensitivity to chip design.
    Type: Grant
    Filed: July 28, 1993
    Date of Patent: February 27, 1996
    Assignee: Digital Equipment Corporation
    Inventors: Steven S. Cooperman, Andre I. Nasr
  • Patent number: 5492858
    Abstract: Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where shallow trench isolation techniques are employed. The etched trenches are first coated with a silicon nitride protective liner before the trenches and active area mesas are conformally coated with a layer of silicon oxide. The conformal oxide then is steam annealed to densify the conformal oxide, and then the surface of the silicon wafer is etched and polished back down to the tops of the active area mesas, to form a substantially planar surface.
    Type: Grant
    Filed: April 20, 1994
    Date of Patent: February 20, 1996
    Assignee: Digital Equipment Corporation
    Inventors: Amitava Bose, Marion M. Garver, Andre I. Nasr, Steven S. Cooperman
  • Patent number: 5346584
    Abstract: Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where trench isolation techniques are employed. The trenches and active areas on a semiconductor substrate are conformally coated with a layer of silicon oxide. A layer of patterned polysilicon then is deposited on top of the oxide and etched to create filler blocks in depressions above the trenches. Next, the polysilicon is annealed to thereby fill the trenches with an expanded oxide block. The resulting relatively planar surface then is polished back to the nitride cap, to thereby produce a high degree of planarity across all trench and active area dimensions.
    Type: Grant
    Filed: July 28, 1993
    Date of Patent: September 13, 1994
    Assignee: Digital Equipment Corporation
    Inventors: Andre I. Nasr, Steven S. Cooperman