Abstract: A system is provided for determining a loading location of a workpiece relative to a holding fixture, comprising: a robot including a sensor; and a controller coupled to the robot and configured to activate the robot to grip the workpiece; enable a free-drive mode to permit an operator to move the gripped workpiece to a starting location; execute a center location routine including causing the robot to: move in a first direction until the sensor senses contact with a first surface of the holding fixture; move in a second direction until the sensor senses contact with a second surface; move in a third direction until the sensor senses contact with a third surface; and compute a three-dimensional center point of the holding fixture representing the loading location of the workpiece using the first, second and third sensed positions of contact.

Abstract: A method for fabricating thick metal integrated transmission lines and circuit topologies for microwave integrated circuits. Microstrip or coplanar waveguide (CPW) transmission line and circuit topologies may be fabricated on semiconductor or dielectric substrates. For microstrip transmission line topologies, a metal ground plane is applied to the opposite side of the substrate from the thick metal transmission line conductor structures. To fabricate a thick metal transmission line topology, a metal plating base is applied to a substrate surface. A photoresist layer, which may include a preformed photoresist sheet, is then applied over the plating base layer. The photoresist layer is exposed to X-rays, such as from a synchrotron, through a mask having an X-ray absorber pattern that defines the desired transmission line or circuit topology. The photoresist layer is then developed to remove sections of the photoresist layer corresponding to the mask pattern and to expose portions of the plating base layer.

Abstract: A practical, low-cost and low hazard method and apparatus for the fabrication of ultra large scale integrated circuits is provided. Plasma source ion implantation (PSII) is employed for realizing required ultra-shallow doping junctions, while avoiding previous difficulties and costs associated with PSII of dopant containing plasmas generated from hazardous gases. The invention makes use of solid boron sources, such as boron carbide (B.sub.4 C), for p-type doping, and solid phosphorus sources, such as red phosphorus, for n-type doping. The solid dopant sources are both stable and relatively inexpensive. Thin layers of p-type or n-type material are deposited on the surface of a semiconductor substrate, such as of Si, by sputtering or vaporization of the solid dopant source material. PSII using a plasma generated from a non-reactive gas, such as argon, is then used to drive the deposited dopant atoms into the surface of the substrate.