Abstract: The present invention describes methods and processes for the production of proteins, particularly glycoproteins, by animal cell or mammalian cell culture, preferably, but not limited to, fed-batch cell cultures. In one aspect, the methods comprise at least two temperature shifts performed during the culturing period, in which the temperature is lower at the end of the culturing period than at the time of initial cell culture. Throughout their duration, the culturing processes of the invention involving two or more downward shifts in temperature sustain a high viability of the cultured cells, and can yield an increased end titer of protein product, and a high quality of protein product, as determined, e.g., by sialic acid content of the produced protein. In another aspect, the methods comprise the delayed addition of polyanionic compound during the culturing period.

Abstract: The present invention describes methods and processes for the production of proteins, particularly glycoproteins, by animal cell or mammalian cell culture, preferably, but not limited to, fed-batch cell cultures. In one aspect, the methods comprise at least two temperature shifts performed during the culturing period, in which the temperature is lower at the end of the culturing period than at the time of initial cell culture. Throughout their duration, the culturing processes of the invention involving two or more downward shifts in temperature sustain a high viability of the cultured cells, and can yield an increased end titer of protein product, and a high quality of protein product, as determined, e.g., by sialic acid content of the produced protein. In another aspect, the methods comprise the delayed addition of polyanionic compound during the culturing period.

Abstract: The present invention describes methods and processes for the production of proteins, particularly glycoproteins, by animal cell or mammalian cell culture, illustratively, but not limited to, fed-batch cell cultures. The methods comprise feeding the cells with D-galactose, preferably with feed medium containing D-galactose, preferably daily, to sustain a sialylation effective level of D-galactose in the culture for its duration, thus increasing sialylation of the produced proteins. The methods can also comprise at least two temperature shifts performed during the culturing period, in which the temperature is lower at the end of the culturing period than at the time of initial cell culture. The cell culture processes of the invention involving two or more temperature shifts sustain a high cell viability, and can allow for an extended protein production phase. The methods can also comprise the delayed addition of polyanionic compound at a time after innoculation.

Abstract: The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

Abstract: The present invention describes methods and processes for the production of proteins, particularly glycoproteins, by animal cell or mammalian cell culture, illustratively, but not limited to, fed-batch cell cultures. The methods comprise feeding the cells with D-galactose, preferably with feed medium containing D-galactose, preferably daily, to sustain a sialylation effective level of D-galactose in the culture for its duration, thus increasing sialylation of the produced proteins. The methods can also comprise at least two temperature shifts performed during the culturing period, in which the temperature is lower at the end of the culturing period than at the time of initial cell culture. The cell culture processes of the invention involving two or more temperature shifts sustain a high cell viability, and can allow for an extended protein production phase. The methods can also comprise the delayed addition of polyanionic compound at a time after innoculation.

Abstract: The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

Abstract: There is disclosed a process for purifying a natural product using a two-phase, multi-solvent system followed by vacuum concentration and back extraction. The method allows for the removal of impurities by controlling the polarity balance of a two-phase system by manipulating the proportions of the four solvents and subsequently the relative distribution of the product versus the impurities.

Abstract: The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

Abstract: There is disclosed a process for purifying a natural product using a two-phase, multi-solvent system followed by vacuum concentration and back extraction. The method allows for the removal of impurities by controlling the polarity balance of a two-phase system by manipulating the proportions of the four solvents and subsequently the relative distribution of the product versus the impurities.

Abstract: An optical position indicator includes a stationary base; a member having a longitudinal axis, the member being displaceable with respect to the stationary base along the longitudinal axis between a first position and a second position, the member including a reflective notch having two sides, the two sides defining respective planes that intersect the longitudinal axis at 45 degree angles; a light source; a first optical fiber mounted on the stationary base, the first optical fiber having a receiving end for receiving light from the light source and an illuminating end for illuminating the notch with a conical beam of light, the conical beam of light having a central axis and being completely intersected by one of the two sides of the notch, the central axis of the conical beam of light being perpendicular to the longitudinal axis of the member; a second optical fiber mounted on the stationary base, the second optical fiber having a receiving end for receiving light reflected from the notch when the member i

Abstract: The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

Abstract: A process for fabricating a bipolar transistor on a silicon-on-insulator substrate which includes etching a bipolar transistor area into the substrate, wherein the bipolar transistor area has substantially vertical sidewalls and a bottom, and forming a buried collector in bottom of the bipolar transistor area. Polysilicon sidewalls are formed adjacent to the vertical sidewalls in the bipolar transistor area, wherein the polysilicon sidewalls are connected to the buried collector. The polysilicon sidewalls are oxidized to form a layer of oxidized polysilicon. Oxide sidewalls are formed on the oxidized polysilicon sidewalls, and epitaxial silicon is formed to fill the bipolar transistor area. A base and an emitter are formed for the bipolar transistor, within the epitaxial barrier.

Abstract: A fusible link and method for its fabrication. A polysilicon pad is formed on top of an insulating layer and covered with a second insulating layer. A trench is selectively etched into the second insulating layer exposing the top of the polysilicon pad. An fusible aluminum link is then formed over the second insulating layer and trench and conformal therewith. When a programming current is driven through the link, the aluminum melts and is absorbed by the polysilicon pad, thereby preventing the link's growback.

Abstract: A process for fabricating a bipolar transistor on a silicon-on-insulator substrate which includes etching a bipolar transistor area into the substrate, wherein the bipolar transistor area has substantially vertical sidewalls and a bottom, and forming a buried collector in bottom of the bipolar transistor area. Polysilicon sidewalls are formed adjacent to the vertical sidewalls in the bipolar transistor area, wherein the polysilicon sidewalls are connected to the buried collector. The polysilicon sidewalls are oxidized to form a layer of oxidized polysilicon. Oxide sidewalls are formed on the oxidized polysilicon sidewalls, and epitaxial silicon is formed to fill the bipolar transistor area. A base and an emitter are formed for the bipolar transistor, within the epitaxial barrier.

Abstract: An Internet high fidelity audio transmission and compression protocol including a system for representing synthesized music in a relatively small file as compared to digital recording. The protocol includes a method for streaming the transmission of a music data file from a Server-Composer computer such that the music can begin being played back as soon as the file begins to arrive at a Client-Player computer. The system includes a graduated resolution improvement feature which allows the music to be recreated exactly as originally composed as the necessary wavetable data is downloading in the background and the music continues to play in the foreground.

Abstract: A method of planarizing a non-planar substrate, such as filling vias and contact holes, spreads a suspension of a conducting material suspended in a liquid on a substrate. The suspension includes an organometallic material, preferably with particles of a polymerized tin or indium alkoxide. The material is spread by spinning the substrate after applying the suspension. The carrier liquid and organic groups are removed by baking and curing at elevated temperatures, thereby depositing the conductive material on the substrate in a layer which is more planar than the substrate and which has regions of greater and lesser thickness. A relatively brief etch step removes conductive material from regions of lesser thickness, leaving material filling vias or contact holes.

Abstract: A semiconductor fuse and method for fabricating the same An insulating layer is provided and a trench formed therein. A fusible link is then formed across the insulating layer and trench and conformal therewith. The link has a break region of minimum thickness and width at an intersection of a sidewall and bottom surface of the trench.

Abstract: An ink-jet print head comprises an ink drive unit formed on a first substrate and an ink reservoir unit formed on a second substrate. The ink drive unit includes a thin film piezoelectric transducer formed on one side of the substrate. The reservoir unit includes an etched cavity in the substrate for forming an ink reservoir, the cavity having an aperture in the base extending through the substrate to form an ink nozzle. The ink drive and ink reservoir units are bonded together with the piezoelectric transducer within the ink reservoir. Activating the transducer expels ink from the reservoir via the ink nozzle.

Abstract: A process for forming a titanium silicide local interconnect between electrodes separated by a dielectric insulator on an integrated circuit. A first layer of titanium is formed on the insulator, and a layer of silicon is formed on the titanium. The silicon layer is masked and etched to form a silicon strip connecting the electrodes, and an overlying second layer of titanium is formed over the silicon strip. The titanium and silicon are heated to form nonsilicidized titanium over a strip of titanium silicide, and the nonsilicidized titanium is removed.

Abstract: An apparatus for and method of scanning a key array (101-116) uses two or three scan lines (134 and 135 or 308, 309, and 310), thereby limiting the need for an excessive number of input/output lines of a processor (136). A separate resistor ladder (301,302, 303) is provided for each dimension of keys, including row, column, and/or matrix. A minimal number of parts is also required to implement the resistor ladder (301,302, 303). A reference conductor (311), a row conductor (312), a column conductor (313), and, if desired, a matrix conductor (314) each run under each key, such that when a different key is depressed, a unique combination of voltages appears at the scan lines (134 and 135 or 308, 309, and 310) for the resistor ladders (301, 302, 303).