Abstract: An interactive electromigration rule-based topography layout adjustment methodology is provided as an adjunct to a computer aided design tool, in particular a design rule check (DRC) mechanism, the engine for which is served by a design rule database for defining topography parameters that conform with a given semiconductor wafer fabrication process. Using a set of customized design rule statements, the DRC program is able to provide circuit designer with the ability to identify and interactively change, as necessary, dimensions of those portions of branches of interconnect (metal, contacts, vias) within the topography of an integrated circuit layout, the customized DRC statements being customized in accordance with circuit operation-derived worst case current conditions as applied to a prescribed set of electromigration-based minimum width rules for interconnect metal, contacts and vias.