Abstract: A management capability is provided for a virtual computing platform. In one example, this platform allows interconnected physical resources such as processors, memory, network interfaces and storage interfaces to be abstracted and mapped to virtual resources (e.g., virtual mainframes, virtual partitions). Virtual resources contained in a virtual partition can be assembled into virtual servers that execute a guest operating system (e.g., Linux). In one example, the abstraction is unique in that any resource is available to any virtual server regardless of the physical boundaries that separate the resources. For example, any number of physical processors or any amount of physical memory can be used by a virtual server even if these resources span different nodes.

Abstract: A communications controller of a data processing system uses a microprocessor to control communication operations. Apparatus in the controller stretches the microprocessor clock cycle signals for selected operations to allow the microprocessor speed to match the speed of the logic performing the selected operation. The apparatus includes a counter which is freerunning for the stretched cycle and reset on a predetermined cycle for the "no stretch" cycle. A decoder coupled to the counter conditions logic gates to generate the microprocessor clock cycle signals.

Abstract: A data processing system operating in a bit oriented protocol (BOP) mode of operation senses a transmit underrun; that is, the subsystem is not receiving data from a microprocessor fast enough to maintain the synchronous transmission over the communication line. Apparatus senses the transmit underrun state and generates an abort sequence of bits containing from 8 to 13 successive binary ONE bits.

Abstract: A data processing system having a communications subsystem operating in a byte control protocol mode includes apparatus for establishing byte synchronization between the data circuit terminating equipment (DCE) and the communications subsystem. The apparatus includes a flop for receiving a stream of predetermined binary bits, a counter generating count signals indicative of the number of binary bits between a byte timing signal from the DCE and the last binary ONE bit of the last byte containing all binary ONE bits, a shift register for the serial shifting of the transmitted data bits and a multiplexer responsive to the count signals for selecting the shift register terminal, thereby timing the byte timing signal to the binary bit stream of data bits, including bytes of all binary ONE bits and a byte of all binary ZERO bits, followed by bytes of data bits.

Abstract: A communications subsystem having a microprocessor coupled to an address bus and a data bus includes a latching register also coupled to the address bus and the data bus. The latching register is responsive to signals from the data bus and address bus for storing bits representative of a direct connect mode, a clear to send mode, and a bit oriented or byte control protocol mode.

Abstract: A data processing system includes a communications subsystem communicating with a number of devices. A counter monitors the communication line to detect when a communication line goes idle, that is at least 15 successive binary ONE bits appear on the line for the bit oriented protocol mode. The counter advances on successive binary ONE bits and is forced to a hexadecimal ZERO in response to a binary ZERO. If the counter reaches a count of hexadecimal F (decimal 15) a carry signal from the counter prevents the counter from advancing and initiates an idle link state.