Abstract: Compounds, and pharmaceutically acceptable salts thereof, useful as inhibitors of sodium channels are provided. Also provided are pharmaceutical compositions comprising the compounds or pharmaceutically acceptable salts and methods of using the compounds, pharmaceutically acceptable salts, and pharmaceutical compositions in the treatment of various disorders, including pain.

Abstract: Systems and methods for forecasting behavior of caches include a hypothetical cache. The hypothetical cache is configured to emulate cache behavior, and performance metrics for the hypothetical cache are determined, where the performance metrics may be based on cache hits/misses. Performance metrics for a real cache of a processor core of a processing system may also be similarly determined. Behavior of the real cache is forecast based, at least, on performance metrics of the hypothetical cache, and in some cases, also on performance metrics of the real cache (e.g., based on a comparison of the performance metrics). Actions may be recommended and/or performed based on the forecast, where the actions include modifying the real cache size, associativity, or allocation for processor cores, migrating a task running in one processor cluster to another processor cluster, or for collecting data for the real cache for offline analysis.

Abstract: A method of dynamically controlling power within a multicore CPU is disclosed and may include receiving a degree of parallelism in a workload of a zeroth core and determining whether the degree of parallelism in the workload of the zeroth core is equal to a first wake condition. Further, the method may include determining a time duration for which the first wake condition is met when the degree of parallelism in the workload of the zeroth core is equal to the first wake condition and determining whether the time duration is equal to a first confirm wake condition. The method may also include invoking an operating system to power up a first core when the time duration is equal to the first confirm wake condition.

Abstract: Systems and methods for forecasting behavior of caches include a hypothetical cache. The hypothetical cache is configured to emulate cache behavior, and performance metrics for the hypothetical cache are determined, where the performance metrics may be based on cache hits/misses. Performance metrics for a real cache of a processor core of a processing system may also be similarly determined Behavior of the real cache is forecast based, at least, on performance metrics of the hypothetical cache, and in some cases, also on performance metrics of the real cache (e.g., based on a comparison of the performance metrics). Actions may be recommended and/or performed based on the forecast, where the actions include modifying the real cache size, associativity, or allocation for processor cores, migrating a task running in one processor cluster to another processor cluster, or for collecting data for the real cache for offline analysis.

Abstract: The various aspects provide for a device and methods for intelligent multicore control of a plurality of processor cores of a multicore integrated circuit. The aspects may identify and activate an optimal set of processor cores to achieve the lowest level power consumption for a given workload or the highest performance for a given power budget. The optimal set of processor cores may be the number of active processor cores or a designation of specific active processor cores. When a temperature reading of the processor cores is below a threshold, a set of processor cores may be selected to provide the lowest power consumption for the given workload. When the temperature reading of the processor cores is above the threshold, a set processor cores may be selected to provide the best performance for a given power budget.

Abstract: Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees for a group of processors to ensure that the processors does not remain in a busy state (e.g., due to transient workloads) for a combined period that is more than a predetermined amount of time above that which is required for one of the processors to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of one or more of the processors based on a variable delay to ensure that the multiprocessor system only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processors.

Abstract: A method of dynamically controlling power within a central processing unit is disclosed and may include entering an idle state, reviewing a previous busy cycle immediately prior to the idle state, and based on the previous busy cycle determining a CPU frequency for a next busy cycle.

Abstract: Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees to ensure that a processor does not remain in a busy state (e.g., due to transient workloads) for more than a predetermined amount of time above that which is required for that processor to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of a processor based on a variable delay to ensure that the processing core only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processor.

Abstract: Devices and methods for monitoring one or more central processing units in real time are disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings. A device may include means for monitoring state data associated with the one or more CPUs in real-time, means for filtering the state data, and means for selectively altering one or more system settings at least partially based on filtered state data. A device may also include a sub-sampling circuit configured to receive a hardware core signal from the central processing unit and output a central processing unit state indication, and an infinite impulse response filter connected to the sub-sampling circuit and configured to receive the central processing unit state indication from the sub-sampling circuit.

Abstract: Methods and apparatus for accomplishing dynamic frequency/voltage control between at least two processor cores in a multi-processor device or system include receiving busy, idle and wait, time and/or frequency information from a first processor core and receiving busy, idle, wait, time and/or frequency information from a second processor core. The received busy, idle, wait, time and/or frequency information may be correlated to identify patterns of interdependence. The correlated information may be used to determine dynamic frequency/voltage control settings for the first and second processor cores to provide a performance level that accommodates interdependent processes, threads and processor cores. The correlation of received busy, idle, wait, time and/or frequency information may involve generating a consolidated busy/idle pulse train that can then be used to set the frequency or voltage of each processor core independently.

Abstract: A method of controlling power within a multicore central processing unit (CPU) is disclosed. The method may include monitoring a die temperature, determining a degree of parallelism within a workload of the CPU, and powering one or more cores of the CPU up or down based on the degree of parallelism, the die temperature, or a combination thereof.

Abstract: A method and system for managing bandwidth demand for a variable bandwidth processing element in a portable computing device (“PCD”) includes monitoring bandwidth requests of a plurality of constant bandwidth processing elements and monitoring bandwidth requests of a variable bandwidth processing element. The variable bandwidth processing element may be either a graphics processing unit (GPU) or a central processing unit (CPU). The method may include determining if the variable bandwidth processing element needs adjustment to its bandwidth for a bus. Next, a message may be communicated to an aggregate bus driver indicating a level of adjustment for the variable bandwidth processing element. Based on the minimum frequency set for the entire PCD and the level of adjustment for the variable bandwidth processing element, the aggregate bus driver may set a new bandwidth value for the predetermined threshold of the bandwidth limiter for the variable bandwidth processing element.

Abstract: The various aspects provide for a device and methods for intelligent multicore control of a plurality of processor cores of a multicore integrated circuit. The aspects may identify and activate an optimal set of processor cores to achieve the lowest level power consumption for a given workload or the highest performance for a given power budget. The optimal set of processor cores may be the number of active processor cores or a designation of specific active processor cores. When a temperature reading of the processor cores is below a threshold, a set of processor cores may be selected to provide the lowest power consumption for the given workload. When the temperature reading of the processor cores is above the threshold, a set processor cores may be selected to provide the best performance for a given power budget.

Abstract: A method of controlling power at a central processing unit is disclosed. The method may include moving to a higher CPU frequency after a transient performance deadline has expired, entering an idle state, and resetting the transient performance deadline based on an effective transient budget.

Abstract: A method and system for executing a plurality of threads are described. The method may include mapping a thread specified priority value associated with a dormant thread to a thread quantized priority value associated with the dormant thread if the dormant thread becomes ready to run. The method may further include adding the dormant thread to a ready to run queue and updating the thread quantized priority value. A thread quantum value associated with the dormant thread may also be updated, or a combination of the quantum value and quantized priority value may be both updated.

Abstract: A method of controlling power within a multicore central processing unit (CPU) is disclosed. The method may include monitoring a die temperature, determining a degree of parallelism within a workload of the CPU, and powering one or more cores of the CPU up or down based on the degree of parallelism, the die temperature, or a combination thereof.

Abstract: A method of controlling power within a multicore central processing unit (CPU) is disclosed. The method may include monitoring a die temperature, determining a degree of parallelism within a workload of the CPU, and powering one or more cores of the CPU up or down based on the degree of parallelism, the die temperature, or a combination thereof.

Abstract: PourOver is the process of replicating databases across clusters, in order to achieve real and/or near real-time database consistency between clusters (e.g., continually provide the ability to construct a consistent database on the alternate cluster that is up to date within a few minutes worth of transactions).

Abstract: A method of controlling core clocks in a multicore central processing unit is disclosed and may include executing a zeroth dynamic clock and voltage scaling (DCVS) algorithm on a zeroth core and executing a first DCVS algorithm on a first core. The zeroth DCVS algorithm may operable to independently control a zeroth clock frequency associated with the zeroth core and the first DCVS algorithm may be operable to independently control a first clock frequency associated with the first core.

Abstract: A method of dynamically controlling power within a multicore central processing unit is disclosed and includes executing a plurality of virtual cores, virtually executing one or more tasks, one or more threads, or a combination thereof at the virtual cores, and physically executing one or more tasks, one or more threads, or a combination thereof at a zeroth physical core. The method may further include receiving a degree of parallelism in a workload of a plurality of virtual cores and determining whether the degree of parallelism in the workload of the virtual cores is equal to a first wake condition.